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STC5455 Datasheet(PDF) 27 Page - Connor-Winfield Corporation |
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STC5455 Datasheet(HTML) 27 Page - Connor-Winfield Corporation |
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27 / 56 page ![]() Page 27 of 56 TM121 Rev:P1.3 Date: October 24, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5455 Synchronous Clock for SETS Data sheet Preliminary Figure 10:SPI Bus Timing, Write access Table 7: SPI Bus Timing Symbol Description Min Max Unit tCS CS low to SCLK high 10 ns tCH SCLK high time 50 ns tCL SCLK low time 50 ns tDs Data setup time 10 ns tDh Data hold time 10 ns tDRDY Data ready 7 ns tDHLD Data hold 3 ns tCSHLD CS hold 30 ns tCSTRI CS off to data tri-state 5 ns tCSMIN Minimum delay between successive accesses 50 ns CS SCLK SDI tDs 1 2 3 4 A6 A5 A4 A3 A2 A1 A0 5 6 7 8 13 14 15 16 9 10 11 12 0 tDh MSB LSB tCL tCH tCS D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB tCSMIN tCSHLD |
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