RF69 datasheet(55/81 Pages) ETC2

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RF69

Page 54

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The transmission of packet data is initiated by the Packet Handler only if the chip is in Tx mode and the transmission

condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a

preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or

one until the condition is met to transmit the packet data.

The transmission condition itself is defined as:

 if TxStartCondition = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the

preamble followed by the sync word and user payload

 If TxStartCondition = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number

defined in RegFifoThresh + 1

 If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of

packet starts immediately on enabling Tx

5.5.4. Rx Processing (without AES)

In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:

 Receiving the preamble and stripping it off

 Detecting the Sync word and stripping it off

 Optional DC-free decoding of data

 Optionally checking the address byte

 Optionally checking CRC and reflecting the result on CrcOk.

Only the payload (including optional address and length fields) is made available in the FIFO.

When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed

length packet format is enabled then the number of bytes received as the payload is given by the PayloadLength

parameter.

In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The

internal length counter is initialized to this received length. The PayloadLength register is set to a value which is greater

than the maximum expected length of the received packet. If the received length is greater than the maximum length stored

in PayloadLength register the packet is discarded otherwise the complete packet is received.

If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed

length is the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues

otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the

CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the

FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode.

If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by

setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC

fails.

5.5.5. AES

AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed

can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which

retains its value in Sleep mode.

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