AS1860 datasheet(20/51 Pages) ETC2

20 / 51 page

AS1860

Akros Silicon, Inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



http://www.AkrosSilicon.com

PD CONTROLLER

Figure 9 - AS1860 PD Controller Block Diagram

The AS1860 contains a fully integrated PD Controller (see

Figure 9) that meets all system requirements for the IEEE®

802.3 standard for Ethernet, and, all PD power management

requirements for IEEE® Standards 802.3af and 802.3at and

for the emerging 60/90W standard. 60W/90W power delivery

can be implemented in a number of ways using the AS1860’s

flexible architecture. See the Power over Ethernet overview

on page 43 in this datasheet for additional PoE information.

PD Power MOSFET

Ethernet power source current is controlled with an

integrated low-leakage, low RDSON, NMOS power MOSFET

that is used to connect the 48RTN and 48N ground planes. If

necessary the FET is throttled back or switched off to protect

the AS1860 from damage due to problematic voltage,

current, or temperature related conditions. For power levels

greater than the AF or AT standards, an external power FET

is placed in parallel with the internal FET. Gate control of this

external FET is detailed in the 60/90W applications section.

Under-voltage Lockout (UVLO)

The UVLO circuitry detects low power source voltage

conditions and disconnects the power MOSFET to protect

the PD (see full power voltage activation and deactivation

threshold specifications in the PD Electrical Characteristics).

PoE Current Limit/Current Sense

Current Limit/Current Sense circuitry minimizes on-device

temperature peaks by limiting both inrush current and

operating current. It monitors the current via an integrated

sense circuit that regulates the gate voltage to the PD Power

MOSFET.

This inrush current limiting maintains the cable voltage above

the turn-off threshold as the input capacitor charges, an

action that aids in preventing the PSE from going into current

limit mode.

The PoE current limit is set by the CLIM input pin during PoE

operating modes. When CLIM is set Low (48RTN) current is

limited to 350mA (min); when High, 720mA (min). If the

maximum primary current is exceeded, control of the internal

PD Power MOSFET is used to protect the system from

overload. In Local Power mode (LDET active), this CLIM

based current control is not used (primary side external FET

sensed current control can always be used).

Over-temperature Protection

If die temperature exceeds 140°C (typ) the AS1860 is shut

down. Power is automatically reapplied when the die

temperature returns to 100°C (typ).

PD Operating States

The AS1860 has five states of PD operation:

–

Reset

- The classification state machine is reset, and

all circuitry blocks are disabled.

–

Signature Detection

- The PD signature resistance is

applied across the input.

–

Classification

- The AS1860 indicates power

requirements to the PSE.

–

Idle

- This state is entered after classification, where it

remains until full-power input voltage is applied.

–

- The PD is enabled, and supplies power to the

DC-DC controller and the local application circuitry. In

this state the PD also provides a Maintain Power

Signature (MPS) state as required by the IEEE® PoE

standard.

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