AS1860 datasheet(27/51 Pages) ETC2

27 / 51 page

AS1860

Akros Silicon, Inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



http://www.AkrosSilicon.com

Current-Limit and Current Sense

The Controller provides cycle-by-cycle current limiting to

ensure that current limits are not exceeded, using an external

resistor sensed at ISENP4 and ISENN4.

For each PWM cycle during which the maximum ISENP4-to-

ISENN4 sensed current limit voltage is tripped, a short-circuit

counter is incremented. This counter is reset to zero if and

only if two consecutive PWM cycles do not contain current

limit events. If the counter reaches 16 a short-circuit event is

declared and Output #4 is powered down. After 256 clock

cycles of wait time Output #4 will attempt a restart, if the

short-circuit persists the counter will begin to increment and

the cycle will repeat itself.

Over-voltage Protection

Output #4 has a built-in over-voltage monitor set to +10% of

nominal voltage. If tripped the output is shut down until within

+5% of nominal voltage, normal operation is then resumed.

If Voltage Margining is used (see Software Mode Operation)

the over-voltage protection tracks to the margining selected.

HARDWARE MODE OPERATION

The Hardware mode of operation is designed to provide

basic control and status of the device via hardware (pin)

control signals. Hardware mode functions and operation are

described below.

(Please also refer to the Akros document AN080 for a

detailed Design Guide.)

Device

Initialization

Hardware

Mode

Selection

Primary-side digital logic is initialized while the MODE pin is

Low, A required external capacitor between MODE and 48N

provides the power-on reset input required to initialize the

device.

Hardware (HW) mode is selected when the MODE pin is also

pulled-up High (in addition to the power-on reset capacitor to

48N). The VDD3V_OUT pin can be used for the MODE pin

pull-up power source by using a 17.8KΩ (maximum) resistor

from MODE to VDD3V_OUT.

Secondary-side digital logic is initialized while the SEC_EN

pin is Low, a required external capacitor between SEC_EN

and SGND will provide the power-on reset input required to

initialize the secondary-side.

HW Mode Power Output Controls

Power Outputs #2 thru #4 each have independent output

enable pins (EN2, EN3, and EN4) that enable the

corresponding power output, and, can also be used to delay

the power outputs relative to each other. Note that Output #1,

the main device power output, is always enabled and does

not have an output enable pin.

The ENx pins have internal pull-ups, so outputs are enabled

when an ENx pin is simply connected to an external timing

capacitor (CENX), see Figure 16.

As shown in Figure 17, a Low voltage (ground) on an ENx

pin disables the corresponding power output. In addition, if

an output is not used the associated FBx pin should in fact

be pulled High to prevent a disabled output from affecting

PGOOD status.

Figure 16 - HW Mode Output(s) Hardware Enabled

Figure 17 - HW Mode Output(s) Hardware Disabled

HW Mode Power Output Sequencing

Connecting a grounded external capacitor to an ENx pin

establishes a delay before the corresponding power output is

turned on. Each power output delay capacitor can be

selected to create a user defined power-on sequence.

The time delay (TENX) in seconds for a capacitor (CENX) is

defined by the formula:



ENX



(must be > 8ms)

For example, a 200nF cap creates an output delay of 16ms.

Each ENx pin has an internal 0.8V threshold detector and

sources 10µA. When the ENx pin reaches 0.8V, enable delay

timing begins.

Each ENx delay must be greater than 8ms for proper device

startup assuming a typical 10nF capacitor on SEC_EN. All

delays for power outputs #2-#4 are synchronized to the

beginning of the Output #1 voltage ramp (see Figure 18).

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