AS1860 datasheet(8/51 Pages) ETC2

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AS1860

Akros Silicon, Inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



http://www.AkrosSilicon.com

Table 2 - AS1860 Signal Descriptions - Secondary Side

Name

I/O1

Description

Secondary-Side: Common Power Pins

Paddle

SGND

Secondary-side ground connection. One of three bottom side device connections, SGND

(Paddle #3) is the Secondary-side ground connection.

37, 38

#2, #3, #4 DC-DC regulators and controller power inputs, internally connected together. Must

be connected externally to the same source, nominally Output #1

VDD3V_OSEC

Internal Buck power regulator output. Must be decoupled and used for the VDD3V_ISEC (pin

58) power source. VDD3V_OSEC can also be used for additional 3.3V secondary-side

platform power (pull-ups, etc.); see Electrical Characteristics for supply limits.

VDD3V_ISEC

Secondary-side 3.3V power input. This must be sourced from VDD3V_OSEC (pin 46).

Secondary-Side: Synchronous Rectification Controller (Output #1)

VDD_SYNC

Sync FET power decoupling node. Decouple with an external capacitor, VDD_SYNC to

SGND. This node is nominally 5V.

FB1

Controller voltage feedback input.

ISENSES

Controller secondary-side sync switches node current sense. Sensed signal is used to

control the external secondary-side power FET, making it an efficient power diode.

COMP1

Controller compensation network connection.

SYNC_OUT

Controller sync gate drive output. Used for secondary-side synchronization in conjunction

with the primary-side controller.

AGND1

Controller secondary-side sense ground, used for both differential feedback and differential

current sensing. Should be routed differentially, as the pairs of FB1 & AGND1 and ISENSES

& AGND1.

Secondary-Side: Regulator (Output #2)

AGND2

Sense ground for the Output #2, should be routed together with FB2 for differential feedback

sensing and then tied to ground at the feedback resistor. If Output #2 is not used, AGND2

should still be tied to SGND.

LX2

Regulator switches node output. If Output #2 is not used, float LX2 (no user connection).

FB2

Regulator voltage feedback input, also used to disable Output #2 (see EN2).

MODE

The MODE pin selects the device operation mode at power-on.

For Hardware Mode Operation:

–

Mode 1 = Reset mode

Mode 1 is selected by holding the MODE pin Low (MODE to 48N).

–

Mode 2 = HW Operating Mode

Mode 2 is selected with a pull-up resistor (17.8K

 max) from MODE to

VDD3V_OUT plus a required power-on reset capacitor from MODE to

48N.

For Software Mode Operation:

–

Mode 1 = Reset mode

Mode 1 is selected by holding the MODE pin Low (MODE to 48N).

–

Mode 2 = SW Operating Mode with I²C device address per I2C_ADR pin setting

Mode 2 is selected with a required power-on reset capacitor from MODE

to 48N.

Primary-Side: Miscellaneous

TEST1

Must be pulled down to 48RTN with a resistor (4.7K

-100K).

9, 10

No User Connection. Must be floated.

I = Input, O = Output, I/O = Bidirectional, PU = Internal pull-up, PD = Internal pull-down, P = Power,

A = Analog, D = Digital, OD = Open drain

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