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AS1860 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers

Part # AS1860
Description  60W/90W PoE PD Controllers
PDF  51 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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AS1860 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers

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AS1860
Akros Silicon, Inc.
6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA
408.746.9000
http://www.AkrosSilicon.com
7
14
VDD3V_OUT
P
Primary-side supply voltage source (3.3 volts). This supply can be used for additional
external circuits on the primary side that are referenced to 48N, see Electrical Characteristics
for supply limits.
64
VDD3V_IN
P
Primary-side input supply voltage (3.3 volts) normally connected to VDD3_OUT.
21
VDD5I
P
Low power node that can be used to supply 48RTN referenced devices, see Electrical
Characteristics for supply limits. Must be decoupled with an external capacitor.
23
RB
I, PU
PD Controller state machine Power-on-Reset, connect to 48RTN with external capacitor.
Primary-Side: DC-DC Controller
7
CSS
A
Primary-side PWM Soft Start input, decouple to 48N with an external capacitor.
11
GATE
A
Primary-side external Power FET gate drive.
8
ISENSEP
A
Current sense input, also used to set Primary PWM current limit (with external resistor).
63
SYNC_DLY
A
Along with SYNC_OVL this signal sets Primary and Secondary-side primary sync delay
timing for Output #1. Connecting a resistor to ground (48N) from this input will optimize
output efficiency for a given PD power level or Sync Power-FET choice. See Table 19 for
resistor value selection and other details.
6
SYNC_OVL
A
Along with SYNC_DLY this signal sets Primary and Secondary-side primary sync overlap
timing for Output #1. Connecting a resistor to ground (48N) from this input will optimize
output efficiency for a given PD power level or Sync Power-FET choice. See Table for
resistor value selection and other details.
Primary-Side: Clock Dividers
2
PRI_DIV
A, I
Primary PWM frequency divider input. Connect an external resistor (5%) from this input to
ground to set the Primary PWM clock divider. Used in either internal or external (if the
CLK_IN input is active) clocking operation.
Note that the Primary PWM clocking rate is a function of both PRI_DIV and SEC_DIV divider
ratios. See Device Description, Figure 4 and Table 17 for details.
62
SEC_DIV
A, I
Secondary PWM frequency divider input. Connect an external resistor (5%) from this input to
ground to set the Secondary PWM clock divider for either internal or external (if the CLK_IN
input is active) PWM clocking operation.
Note that the Secondary PWM clocking rate is a function of this SEC_DIV divider ratio. See
PWM Clock Generation description for details.
Primary-Side: Inputs & Outputs
3
GPIP
I, PU
General purpose digital input on primary side, referenced to 48N. See GPIO operation.
4
GPOP
O
General purpose digital output on primary side, referenced to 48N. See GPIO operation.
20
ADCIN
A, I
General purpose ADC input, referenced to 48RTN.
1
I2C_ADR
A, I
Sets the AS1860 I2C device address. One of 8 possible Device addresses is configured by
connecting a resistor on this input to ground (48N). As a result of the chosen resistor, 3 bits
of available addressing for the device are configured. See Table 20 for resistor values and
other details.
61
WD_MODE
I
Watchdog Timer mode. Enables/disables watchdog timer and sets timer period, operation
also varies with MODE input setup.
For Hardware Mode Operation:
WD_MODE = Low (connect to 48N): watchdog off.
WD_MODE = Capacitor to 48N: A 1 second timeout generates a PGOOD output transition.
WD_MODE = High (connect to VDD3V_OUT): A 32 second timeout generates a PGOOD
output transition.
For Software Mode Operation:
WD_MODE = Low (connect to 48N): watchdog off.
WD_MODE = Capacitor to 48N: Power-on enables watchdog usage and counter starts (at
max count) after PGOOD indicates good power. Use the Watchdog Timeout Register to
change timeout count. Watchdog servicing is via Hardware or I2C commands.
WD_MODE = High (connect to VDD3V_OUT): Power-on enables watchdog usage but waits
for software to enable before starting. Use Watchdog Timeout Register for timeout length
(reset to max). Watchdog servicing is via Hardware pin or I2C commands.



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