AS1860 datasheet(4/51 Pages) ETC2

4 / 51 page

AS1860

Akros Silicon, Inc.

6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA

408.746.9000



http://www.AkrosSilicon.com

FIGURES

Figure 1 - AS1860 Pin Assignments..................................................................................................................................................... 6

Figure 2 - Vin=38V 12V 2.5A Start Up................................................................................................................................................ 18

Figure 3 - Vin=40V_12V_2.5A _Start Up with el load......................................................................................................................... 18

Figure 4 - Vin=57V_12V_3A _Start Up with el load............................................................................................................................ 18

Figure 5 - Vin=48V_12V_3A _Start Up with el load............................................................................................................................ 18

Figure 6 - Vin=48V_12V_3A _Start Up............................................................................................................................................... 18

Figure 7 - Vin=57V_12V_3A _Start Up............................................................................................................................................... 18

Figure 8 - AS1860 Block Diagram ...................................................................................................................................................... 19

Figure 9 - AS1860 PD Controller Block Diagram................................................................................................................................ 20

Figure 10 - PWM Clock Generation Block Diagram............................................................................................................................ 22

Figure 11 - Power Output #1 Block Diagram ...................................................................................................................................... 23

Figure 12 - Power Outputs #2, #3 Block Diagram .............................................................................................................................. 25

Figure 13 - Power Output #4 Block Diagram - BUCK ......................................................................................................................... 26

Figure 14 - Power Output #4 Block Diagram - BOOST ...................................................................................................................... 26

Figure 15 - Power Output #4 Block Diagram - BOOST LED Driver .................................................................................................... 26

Figure 16 - HW Mode Output(s) Hardware Enabled........................................................................................................................... 27

Figure 17 - HW Mode Output(s) Hardware Disabled .......................................................................................................................... 27

Figure 18 - HW Mode Power Output Sequencing Example................................................................................................................ 28

Figure 19 - Hardware Mode PGOOD Generation............................................................................................................................... 28

Figure 20 - Hardware Mode GPIO Pin Mapping ................................................................................................................................. 28

Figure 21 - SW Mode Output(s) Hardware Enabled ........................................................................................................................... 29

Figure 22 - SW Mode Output(s) Hardware Disabled .......................................................................................................................... 29

Figure 23 - SW Mode Power Output Sequencing Example................................................................................................................ 29

Figure 24 - Software Mode PGOOD Generation ................................................................................................................................ 30

Figure 25 - GPIO and ADC Pin Mapping............................................................................................................................................ 31

Figure 26 - I2C Interface Start/Stop and Data Timing ......................................................................................................................... 33

Figure 27 - I2C Acknowledge Timing .................................................................................................................................................. 33

Figure 28 - Device Address/Operation Word...................................................................................................................................... 34

Figure 29 - I2C Interface Write Cycle Timing ...................................................................................................................................... 35

Figure 30 - I2C Interface Read Cycle Timing (with Repeated Start) ................................................................................................... 35

Figure 31 - IEEE® Std. 802.3af Power Feeding Schemes .................................................................................................................. 43

Figure 32 – Four Pair Sensing enabling external MOSFET M1.......................................................................................................... 44

Figure 33 – Primary bias enabling external MOSFET M1 .................................................................................................................. 45

Figure 34 – Secondary side logic control of external MOSFET M1 .................................................................................................... 45

Figure 35 - PoE Power-On Sequence Waveform ............................................................................................................................... 46

Figure 36 - Typical Isolated Synchronous Flyback Application........................................................................................................... 47

Figure 37 - 64-Pin QFN Dimensions................................................................................................................................................... 48

AS1860 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

AS1860 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL