DLPC6401 datasheet(33/50 Pages) TI1

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3.3 V

(VDD33 ASIC I/O)

1.9 V

(VDD_DMD)

1.2 V and 1.8 V

(ASIC PLL)

1.2 V

(VDDC ASIC Core)

POSENSE

1.2 V and 3.3 V

(FPD-Link

VDD12_FPD and

VDD33_FPD)

DLPC6401

www.ti.com

DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015

System Power-Up Sequence (continued)

Figure 16. System Power-Up Sequence

9.3 Power-On Sense (POSENSE) Support

It is difficult to set up a power monitor to trip exactly on the ASIC minimum supply voltage specification. Thus for

practical reasons, TI recommends that the external power monitor generating POSENSE target its threshold to

90% of the minimum supply voltage specifications and ensure that POSENSE remain low a sufficient amount of

time for all supply voltages to reach minimum ASIC requirements and stabilize. Note that the trip voltage for

detecting the loss of power is not critical for POSENSE and thus may be as low as 50% of rated supply voltages.

In addition, the reaction time to respond to a low voltage condition is not critical for POSENSE; however,

PWRGOOD does have much more critical requirements in these areas.

9.4 System Environment and Defaults

9.4.1 DLPC6401 System Power-Up and Reset Default Conditions

Following system power-up, the DLPC6401 device performs a power-up initialization routine that defaults the

ASIC to its normal power mode, in which ARM9-related clocks are enabled at their full rate and associated resets

are released. Most other clocks default to disabled state with associated resets asserted until released by the

processor. These same defaults are also applied as part of all system reset events (watch dog timer timeout, and

so on) that occur without removing or cycling power.

Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it

enables the rest of the ASIC clocks. When system initialization is complete, application software determines if

and when to enter low-power mode.

9.4.2 1.2-V System Power

The DLPC6401 device can support a power delivery system with a single 1.2-V power source derived from a

switching regulator. The DLPC6401 main core should receive 1.2-V power directly from the regulator output and

the internal ASIC PLLs (VDDC, VDD12_PLLD, and VDD12_PLLM) should receive individually-filtered versions

of this 1.2-V power. For specific filter recommendations, see PCB Layout Guidelines for Internal ASIC Power.

9.4.3 1.8-V System Power

A single 1.8-V power source should be used to supply both DLPC6401 internal PLLs. To keep this power as

clean as possible, TI recommends that this power be sourced by a linear regulator that is individually filtered for

each PLL (VDD_18_PLLD and VDD_18PLLM). For specific filter recommendations, see PCB Layout Guidelines

for Internal ASIC Power.

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