DLPC6401 datasheet(4/50 Pages) TI1

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DLPC6401

DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015

www.ti.com

Pin Functions

PIN(1)

I/O (2)

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

CONTROL

External reset output, LOW true. This output is

asserted low immediately upon asserting power-up

reset (POSENSE) low and remains low while

POSENSE remains low. EXT_ARSTZ continues to

be held low after the release of power-up reset (that

is, POSENSE set high) until released by software.

EXT_ARST

H20

VDD33

Async

EXT_ARSTZ is also asserted low approximately 5

µs after the detection of a PWRGOOD or any

internally-generated reset. In all cases, it remains

active for a minimum of 2 ms after the reset

condition is released by software. Note, the ASIC

contains a software register that can be used to

independently drive this output.

Power Good is an active-high signal with hysteresis

that is generated by an external power supply or

voltage monitor. A high value indicates all power is

within operating voltage specifications and the

system is safe to exit its reset state. A transition from

high to low should indicate that the controller or

DMD supply voltage will drop below their rated

minimum level within the next 0.5 ms (POSENSE

must remain active high during this interval). This is

an early warning of an imminent power loss

condition. This warning is required to enhance long-

PWRGOOD

H19

VDDC

Async

term DMD reliability. A DMD park sequence,

followed by a full controller reset, is performed by the

DLPC6401 when PWRGOOD goes low for a

minimum of 4 µs protecting the DMD. This minimum

de-assertion time is used to protect the input from

glitches. Following this, the DLPC6401 is held in its

reset state as long as PWRGOOD is low.

PWRGOOD must be driven high for typical

operation. The DLPC6401 device acknowledges

PWRGOOD as active after it is driven high for a

minimum of 625 ns. Uses hysteresis.

Power-On Sense is an active-high input signal with

hysteresis that is generated by an external voltage

monitor circuit. POSENSE must be driven inactive

(low) when any of the controller supply voltages are

POSENSE

G21

Async

below minimum operating voltage specifications.

POSENSE must be active (high) when all controller

supply voltages remain above minimum

specifications.

Power On or Power Off is an active-high signal that

indicates the power of the system. Power On or

Power Off is high when the system is in power-up

POWER_ON_OFF

N21

VDD33

Async

state, and low when the system is in standby. Power

On or Power Off can also be used to power on or off

an external power supply.

Prior to transferring part of code from parallel flash

content to internal memory, the internal memory is

initialized and a memory test is performed. The

INIT_DONE

F19

VDD33

Async

result of this test (pass or fail) is recorded in the

system status. If memory test fails, the initialization

process is halted. INIT_DONE is asserted twice to

indicate an error situation. See Figure 12.

This signal is sampled during power-up. If the signal

I2C_ADDR_SEL

F21

VDD33

Async

is low, the I2C addresses are 0x34 and 0x35. If the

signal is low, the I2C are 0x3A and 0x3B.

Requires an external pullup to

I2C clock. Bidirectional, open-drain signal. I2C slave

3.3 V. The minimum

I2C1_SCL

VDD33

N/A

clock input from the external processor. This bus

acceptable pullup value is

supports 400 kHz.

1 k

Ω.

Requires an external pullup to

I2C data. Bidirectional, open-drain signal. I2C slave

3.3 V. The minimum

I2C1_SDA

VDD33

I2C1_SCL

to accept command or transfer data to and from the

acceptable pullup value is

external processor. This bus supports 400 kHz.

1 k

Ω.

(1)

For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.

(2)

I/O Type: I = Input, O = Output, B = Bidirectional, and H = Hysteresis. See Table 1 for subscript explanation.

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