DLPC6401 datasheet(10/50 Pages) TI1

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DLPC6401

DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015

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Pin Functions (continued)

PIN(1)

I/O (2)

INTERNAL TERMINATION

CLK SYSTEM

DESCRIPTION

NAME

NO.

POWER

TYPE

JTAG, RESET (active low). This pin should be pulled

high (or left unconnected) when the JTAG interface

is in use for boundary scan. Connect this pin to

TRST

V17

VDD33

Includes internal pullup

Async

ground otherwise. Failure to tie this pin low during

normal operation causes startup and initialization

problems.(8)

RTCK

G18

VDD33

N/A

JTAG return clock(9)

Includes internal pull down.

External pulldown

IC Tri-State Enable (active high). Asserting high tri-

ICTSEN

VDD33

Async

recommended for added

states all outputs except the JTAG interface.

protection.

(9)

For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.

Functional Pin Descriptions (Reserved Pins)

PIN(1)

I/O (2)

CLK

INTERNAL TERMINATION

DESCRIPTION

SYSTEM

NAME

NO.

POWER

TYPE

RESERVED

VDD33

Includes internal pulldown

N/A

Connect directly to ground on the PCB.

N22, M22,

RESERVED

VDD33

Includes an internal pulldown

N/A

P19, P20

Reserved(1)

RESERVED

V16

VDD33

Includes an internal pullup

N/A

RESERVED

D1, J2

VDD33

N/A

F1, F2, G2,

RESERVED

VDD33

Includes internal pulldown

N/A

G3, G4

RESERVED

F3, J1, M21

VDD33

N/A

Leave these pins unconnected(1)

H20, M18,

RESERVED

VDD33

N/A

M20

H21, H22,

J19, J20,

RESERVED

VDD33

Includes internal pulldown

N/A

J21, J22,

Reserved(1)

K19, K20

RESERVED

C1, D2, F4

VDD33

N/A

RESERVED

E3, E2

VDD33

—

Async

Reserved

(1)

For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.

(2)

I/O Type: I indicates input, O indicates output, B indicates bidirectional, and H indicates hysteresis. See Table 1 for subscript

explanation.

Table 1. I/O Type Subscript Definition

I/O

ESD STRUCTURE

SUBSCRIPT

DESCRIPTION

3.3-V LVCMOS I/O buffer, with 4-mA drive

ESD diode to VDD33 and GND

3.3-V LVCMOS I/O buffer, with 8-mA drive

ESD diode to VDD33 and GND

3.3-V LVCMOS I/O buffer, with 12-mA drive

ESD diode to VDD33 and GND

3.3-V LVCMOS receiver

ESD diode to VDD33 and GND

3.3-V LVDS receiver (FPD-Link I/F)

ESD diode to VDD33 and GND

None

N/A

1.9-V LPDDR output buffer (DMD I/F)

ESD diode to VDD_DMD and GND

3.3-V I2C with 12-mA sink

ESD diode to VDD33 and GND

OSC 3.3-V I/O compatible LVCMOS

ESD diode to VDD33 and GND

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