UPD1001

DS00001759B-page 8

 2014 Microchip Technology Inc.

2.1.3

32-SQFN SYSTEM LEVEL DIAGRAMS

Figure 2-2 and Figure 2-3 provide typical system level diagrams of the UPD1001 for 32-A (Standard-A receptacle) and

32-B (Standard-B receptacle) applications, respectively.

29

VSEL1_N

30

VSEL2_N

31

VSEL3_N

32

FAULT_N

Exposed Pad

VSS

FIGURE 2-2:

CONFIGURATION 32-A SYSTEM-LEVEL DIAGRAM

TABLE 2-1:

32-SQFN PACKAGE PIN ASSIGNMENTS (CONTINUED)

Pin Number

Configuration 32-A Name

Configuration 32-B Name

Microchip

UPD1001

32-SQFN

Configuration

32-A

SPI_ROM_CLK

SPI_ROM_DI

SPI_ROM_DO

SPI_ROM_CE_N

VSS

PD_EN_N

CHG_EMU_EN

CFG_SEL0

VDDIO

CFG_SEL1

VDDIO

USB

Power

Delivery

Enabled

Standard-A

Receptacle

Port Power

Controller

VDDIO

VMON

IMON

CSA

+

CMP

IFAULT

D+

D-

GND

PD_DETECT 1

VBUS_DISCHARGE

VBUS

Couple/Filter

PD_DATA

PD_ID

PD_DETECT

INSERTION_DETECT

INSERTION_DETECT 2

INSERTION_DETECT 1

SHIELD

35.7k

5.1k

VDDIO

FAULT_N

VSEL0_N

VSEL1_N

VSEL2_N

VSEL3_N