TAS3103 datasheet(108/146 Pages) TI

108 / 146 page

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3.9.1

Dither Seeds

The dither circuit consists of two linear feedback shift registers—LFSR1 and LFSR2. The dither seed subaddress

(0xC7) consists of a byte-wide seed for LFSR1 (bits 7:0) and a byte-wide seed for LFSR2 (bits 15:8). The seeds serve

to define the starting point of each LFSR sequence, but not the feedback structure itself. Each linear feedback shift

frequency of 135.168 MHz [12.288 MHz (MCLKI) x 11 (PLL multiplier)], the 26-bit LFSR has a cycle time of 496.5 ms

(226/135.168 MHz). LFSR1 and LFSR2 use the same feedback structure but different taps for outputting. As long as

the seeds for the two LFSRs are not

±13 counts apart (in which case the two different sets of output taps would

correlate), any set of seed values for LFSR1 and LFSR2 is suitable.

When two or more TAS3103s are powered by the same supply, a concern as to whether or not there is correlation

between the dither data streams on different chips arises. At power turn on, a TAS3103 does not begin the dither

process until reset is deactivated. If the TAS3103s are reset by the internal power good signals from the internal

regulators, the chip-to-chip variance of the logic voltage threshold point at which the power good signal is deactivated

assures, with a high probability, that the dither data streams between chips are uncorrelated. However, when an

external logic-driven reset is applied to the TAS3103s, the probability of correlation between the dither data streams

on different chips after the rest is removed significantly increases. For this reason, the dither seeds have been made

programmable via the I2C bus.

TAS3103 Datasheet(PDF) 108 Page - Texas Instruments