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TAS3103 Datasheet(PDF) 120 Page - Texas Instruments |
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TAS3103 Datasheet(HTML) 120 Page - Texas Instruments |
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120 / 146 page  4−4 4.4.2 Control Signals Over Recommended Operating Conditions (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS tw1(L) Pulse duration, RST low 10 ns tpd1 Propagation delay, PWRDN high to power down state asserted See Note 11 µs tpd2 Propagation delay, PWRDN low to power down state deasserted See Note 12 µs NOTES: 11. The maximum worst case value for tpd1 is given by t pd1_worst_case + 4096 ) GPIOFSCOUNT LRCLK ) 80 Microprocessor_Clock 12. tpd2 is determined by the time it takes the internal digital PLL to reach a locked condition, which, in turn, is governed by the MCLKI/ XTALI frequency and the PLL output frequency. For a 135-MHz PLL output and an MCLKI value of 24.576 MHz, tpd2 is typically 25 µs. For an 11.264-MHz PLL output clock and a 1.024-MHz MCLKI/XTALI master clock, tpd2 is typically 360 µs. PWRDN tw1(L) tpd1 tpd2 RST Figure 4−2. Control Signals Timing Waveforms |
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