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DP83266 Datasheet(PDF) 114 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 114 Page - National Semiconductor (TI) |
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114 / 152 page  70 Control Information (Continued) Address Configuration Register (ACR) This register contains bits for configuring the address swapping logic All bits in this register are set to Zero upon reset Access Rules Address Read Write 11Ah Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 PCKI2 PCKI1 PCKI0 RSWP1 RSWP0 ISWP2 ISWP1 ISWP0 Bit Symbol Description D0 ISWP0 Indicate Swap 0 This bit controls the address swapping logic for Indicate Channel 0 (ICHN0) If this bit is reset no address swapping takes place If this bit is set both Destination (DA) and Source address (SA) fields are swapped from FDDI bit ordering to canonical bit ordering This involves a bit reversal within each byte D1 ISWP1 Indicate Swap 1 This bit controls the address swapping logic for Indicate Channel 1 (ICHN1) If this bit is reset no address swapping takes place If this bit is set both Destination (DA) and Source address (SA) fields are swapped from FDDI bit ordering to canonical bit ordering This involves a bit reversal within each byte D2 ISWP2 Indicate Swap 2 This bit controls the address swapping logic for Indicate Channel 2 (ICHN2) If this bit is reset no address swapping takes place If this bit is set both Destination (DA) and Source address (SA) fields are swapped from FDDI bit ordering to canonical bit ordering This involves a bit reversal within each byte D3 RSWP0 Request Swap 0 This bit controls the address swapping logic for Request Channel 0 (RCHN0) If this bit is reset no address swapping takes place If this bit is set both Destination (DA) and Source address (SA) fields are swapped from canonical bit ordering to FDDI bit ordering This involves a bit reversal within each byte D4 RSWP1 Request Swap 1 This bit controls the address swapping logic for Request Channel 1 (RCHN1) If this bit is reset no address swapping takes place If this bit is set both Destination (DA) and Source address (SA) fields are swapped from canonical bit ordering to FDDI bit ordering This involves a bit reversal within each byte D5 PCKI0 Pack Frames on ICHN0 This bit controls the packing of Frames into Pool Space Pages for Indicate Channel 0 (ICHN0) When the Frame-Per-Page (FPP) bit is set (see ‘‘Indicate Mode Configuration Register (IMR)’’) the MACSI device will cause a page break and start each new Frame in a new Pool Space Buffer Setting the PCKI0 bit selectively disables the Frame-Per-Page mode for ICHN0 If the FPP bit is zero this PCKI0 bit has no effect D6 PCKI1 Pack Frames on ICHN1 This bit controls the packing of Frames into Pool Space Pages for Indicate Channel 1 (ICHN1) When the Frame-Per-Page (FPP) bit is set (see ‘‘Indicate Mode Configuration Register (IMR)’’) the MACSI device will cause a page break and start each new Frame in a new Pool Space Buffer Setting the PCKI1 bit selectively disables the Frame-Per-Page mode for ICHN1 If the FPP bit is zero this PCKI1 bit has no effect D7 PCKI2 Pack Frames on ICHN2 This bit controls the packing of Frames into Pool Space Pages for Indicate Channel 2 (ICHN2) When the Frame-Per-Page (FPP) bit is set (see ‘‘Indicate Mode Configuration Register (IMR)’’) the MACSI device will cause a page break and start each new Frame in a new Pool Space Buffer Setting the PCKI2 bit selectively disables the Frame-Per-Page mode for ICHN2 If the FPP bit is zero this PCKI2 bit has no effect 114 |
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