DP83266 datasheet(115/152 Pages) NSC

115 / 152 page

70 Control Information (Continued)

Request Channel 0 and 1 Configuration Registers 1 (R0CR1 and R1CR1)

The two Request Configuration Registers 1 (R0CR1 and R1CR1) are programmed with additional operational parameters for

each of the Request Channels Other Request Channel parameters are configured in Request Configuration Registers 0 These

registers may only be altered between Requests ie while the particular Request Channel does not have a Request loaded

All bits in these registers are set to Zero upon reset

Access Rules

Address

Read

Write

11B–11Ch

Always

EFT

RES

ETR

Bit

Symbol

Description

ETR

Early Token Request

When this bit is set the MACSI device attempts to capture a token as soon as a

valid Request Descriptor (REQ) is fetched for this channel This allows the user to maintain tight control

over the Token access timing by pacing REQ availability This is useful for certain models of Synchronous

traffic use If this bit is reset the MACSI device will not capture a Token until enough data for this request

has been fetched to reach the Transmit Data FIFO threshold or the end-of-frame is fetched into the FIFO

This bit should normally be reset because this will save ring bandwidth

D6 – D1

RES

Reserved

EFT

Extended FIFO Threshold

This bit is used to extend the number of FIFO thresholds available with the

TT 10 bits in R0CR0 and R1CR0 See ‘‘Request Channel 0 and 1 Configuration Registers 0 (R0CR0 and

R1CR0)’’ The table below shows the thresholds available The MACSI device Transmit Data FIFO is large

enough to hold an entire maximum length FDDI frame The ‘‘End of Frame’’ threshold is used to tell the

MACSI device not to start transmitting until the entire frame has been staged in the FIFO

EFT

TT 1

TT 0

Threshold

8 words

16 words

128 words

256 words

512 words

Reserved

End of Frame

115

DP83266 Datasheet(PDF) 115 Page - National Semiconductor (TI)

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