DP8344B datasheet(44/184 Pages) NSC

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20 CPU Description (Continued)

Internal

The internal interrupts consist of the Transmitter FIFO Emp-

ty TFE interrupt the Line Turn Around LTA interrupt the

Time Out TO interrupt and a user selectable receiver inter-

rupt source The receiver interrupt source is selected from

either the Receiver FIFO Full RFF interrupt the Data

Available DA interrupt or the Receiver Active RA inter-

rupt The receiver interrupt is selected using bits RIS1 and

RIS0 in the Interrupt Control Register

ICR

See the

Section 30 Transceiver for a description of these inter-

rupts

Masking

The BCP uses two levels of interrupt masking a global inter-

rupt mask which affects all interrupts except NMI and indi-

vidual interrupt mask bits Global enabling and disabling of

the interrupts is performed by changing the state of the

Global Interrupt Enable bit

GIE

in ACR

The maskable

interrupts are disabled when GIE is a zero and enabled

when GIE is a one

GIE is a zero after the BCP is reset

GIE is a readwrite register bit and may be changed by

using any instruction that can write to ACR

In addition

the RET RETF and EXX instructions have option fields

which can be used to alter the state of GIE

The EXX

instruction can set or clear GIE as well as leaving it un-

changed The RET and RETF instructions can restore GIE

to the value that was saved on the address stack at the time

the interrupt was recognized These instructions also pro-

vide the options of clearing or setting GIE or leaving it

unchanged

GIE is set to a zero when an interrupt is rec-

ognized by the CPU It is necessary to set GIE to a one if

interrupts are to be recognized within an interrupt routine

The individual interrupt mask bits are located in

ICR

When set to a one bits IM0

IM1

IM2

IM3 and IM4

in ICR mask the receiver interrupt TFE interrupt LTA in-

terrupt BIRQ interrupt and TO interrupt respectively To

enable an interrupt its mask bit must be set to a zero The

interrupts

and

associated

mask

bits

are

shown

Table 2-27 These bits are set to a one when the DP8344 is

reset

Masking interrupts with GIE or the mask bits in ICR pre-

vents the CPU from acknowledging interrupts but does not

prevent the interrupts from occurring Therefore if an inter-

rupt is asserted it will be processed as soon as it is un-

masked by changing GIE to a one andor changing the

appropriate mask bit in ICR to a zero

Priorites

When more than one interrupt is unmasked and asserted

the CPU processes the interrupt with the highest priority

first NMI has the highest priority followed by the receiver

interrupt TFE LTA BIRQ and TO Each time the interrupts

are sampled the highest priority interrupt is processed first

regardless of how long a lower priority interrupt has been

active Interrupt priority is summarized in Table 2-27

TABLE 2-27

ICR Interrupt Mask Bits

and Interrupt Priority

Interrupt

Mask Bit

Priority

NMI

Highest

RFF DA RA

IMO

TFE

IM1

LTA

IM2

BIRQ

IM3

IM4

Lowest

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