DP8344B datasheet(21/184 Pages) NSC

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20 CPU Description (Continued)

Indexed Addressing Modes

Indexed operands involve one of four possible CPU register

pairs referred to as the index registers

Figure 2-4 illustrates

how the index registers map into the CPU Register Set

Note that the index registers are 16 bits wide

Index registers allow for indirect memory addressing and

usually contain data memory addresses

although

the

LJMP instruction can use index registers to hold instruction

memory addresses Most of the instructions that allow

memory indirect addressing (ie the use of index registers)

also allow pre-incrementing post-incrementing or post-dec-

rementing of the index register contents during instruction

execution if desired Table 2-3 lists the notations used for

the index register modes

The index registers are set to zero when the BCP’s RESET

pin is asserted

Index

CPU Register Pair Forming Index Register

(LSB)

R13

R12

8 7

R15

R14

8 7

R17

R16

8 7

R19

R18

8 7

FIGURE 2-4 Index Register Map

Immediate-Relative and Register-Relative

Address Modes

The Immediate-Relative mode adds an unsigned 8-bit im-

mediate number to the index register IZ forming a data byte

address The Register-Relative mode adds the unsigned

8-bit value in the current accumulator A to any one of the

index registers forming a data byte address Both of these

indirect memory addressing modes are available only on the

MOVE instruction Table 2-4 shows the notation used for

these two addressing modes

2133 Instruction Set Overview

The BCP’s RISC instruction set contains seven categories

of instructions Data Movement Integer Arithmetic Logic

Shift-Rotate Comparison Program Flow and Miscellane-

ous

Data Movement Instructions

The MOVE instruction is responsible for all the data transfer

operations that the BCP can perform Moving one byte at a

time five different types of transfer are allowed register to

instruction memory to register and instruction memory to

data memory Table 2-5 lists all the variations of the MOVE

instruction

TABLE 2-3 Index Register Addressing Mode Notations

Notation

Meaning

Index Register Contents Not Changed

Irb

Index Register Contents Post-Decremented

Ira

Index Register Contents Post-Incremented

Index Register Contents Pre-Incremented

mIr

General Notation Indicating that Any of the Above Modes Is Allowed

Note

denotes indirect memory addressing and is part of the instruction syntax

TABLE 2-4 Relative Index Register Mode Notations

Notation

Type of Action Performed to Calculate a Data Memory Address

IZ a n

IZ a Immediate Number (unsigned)

xData Memory Address

Ir a A

Index Register a Current Accumulator (unsigned)

x Data Memory Address

Note

denotes indirect memory addressing and is part of the instruction syntax

TABLE 2-5 Data Movement Instructions

Syntax

Instruction Operation

Addressing Modes

MOVE Rs Rd

xregister

MOVE Rs mIr

xdata memory

MOVE mIr Rd

data memory

xregister

Indexed Register

MOVE Rs Ir a A

xdata memory

MOVE Ir a A Rd

data memory

x register

MOVE rs IZ a n

xdata memory

Limited Register Immediate-Relative

MOVE IZ a n rd

data memory

x register

Immediate-Relative Limited Register

MOVE n rd

instruction memory

xregister

Immediate Limited Register

MOVE n Ir

instruction memory

xdata memory

Immediate Indexed

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