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DP8344B Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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DP8344B Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 184 page  The DP8344B is an enhanced version of the DP8344A exhibiting improved switching performance and additional functionality The device has been been characterized in a number of applications and found to be a compatible replacement for the DP8344A Differences between the DP8344A and DP8344B are noted by shading of the text on the pages of this data sheet For more information refer to Section 66 Note In this document XXX denotes a control or status bit in a register YYY denotes a register Table of Contents 10 COMMUNICATIONS PROCESSOR OVERVIEW 11 Communications Protocols 12 Internal Architecture Overview 13 Timing Overview 14 Data Flow 15 Remote Interface Overview 20 CPU DESCRIPTION 21 CPU Architectural Description 211 Register Set 2111 Banked Registers 2112 Timing Control Registers 2113 Interrupt Control Registers 2114 Timer Registers 2115 Transceiver Registers 2116 Condition CodeRemote Handshaking Register 2117 Index Registers 2118 Stack Registers 212 Timer 2121 Timer Operation 213 Instruction Set 2131 Harvard Architecture Implications 2132 Addressing Modes 2133 Instruction Set Overview 22 Functional Description 221 ALU 222 Timing 223 Interrupts 224 Oscillator 30 TRANSCEIVER 31 Transceiver Architectural Description 311 Protocols 3111 IBM 3270 3112 IBM 3299 3113 IBM 5250 3114 General Purpose 8-Bit 32 Transceiver Functional Description 321 Transmitter 322 Receiver 323 Transceiver Interrupts 324 Protocol Modes 325 Line Interface 3251 3270 Line Interface 3252 5250 Line Interface 40 REMOTE INTERFACE AND ARBITRATION SYSTEM (RIAS) 41 RIAS Architectural Description 411 Remote Arbitration Phases 412 Access Types 413 Interface Modes 414 Execution Control 42 RIAS Functional Description 421 Buffered Read 422 Latched Read 423 Slow Buffered Write 424 Fast Buffered Write 425 Latched Write 426 Remote Rest Time 2 |
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