DP83901A datasheet(41/62 Pages) NSC

41 / 62 page

130 Bus Arbitration and Timing (Continued)

Threshold Detection (Bus Latency)

To assure that no overwriting of data in the FIFO occurs the

FIFO logic flags a FIFO overrun as the 13th byte is written

into the FIFO effectively shortening the FIFO to 13 bytes

The FIFO logic also operates differently in Byte Mode and in

Word Mode In Byte Mode a threshold is indicated when

the na1 byte has entered the FIFO thus with an 8 byte

threshold the SNIC issues Bus Request (BREQ) when the

9th byte has entered the FIFO For Word Mode BREQ is

not generated until the na2 bytes have entered the FIFO

Thus with a 4 word threshold (equivalent to 8 byte thres-

hold) BREQ is issued when the 10th byte has entered the

FIFO The two graphs indicate the maximum allowable bus

latency for Word or Byte transfer modes

The FIFO at the Beginning of Transmit

Before transmitting the SNIC performs a prefetch from

memory to load the FIFO The number of bytes prefetched

is the programmed FIFO threshold The next BREQ is not

issued until after the SNIC actually begins transmitting data

after SFD The Transmit Prefetch diagram illustrates

this process

Transmit Prefetch Timing

TLF10469 – 56

DP83901A Datasheet(PDF) 41 Page - National Semiconductor (TI)