WM8993 datasheet(135/229 Pages) WOLFSON

135 / 229 page

Production Data

WM8993

PD, November 2010, Rev 4.0

135

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R64 (40h)

FLL Control 5

12:7

FLL_FRC_NCO

_VAL

00_0000

Forces the oscillator value

Valid range is 000000 to 111111

0x19h (011001) = 12MHz approx

(Note that this field is required for free-

running FLL modes only)

FLL_FRC_NCO

FLL control select

0 = controlled by digital loop (default)

1 = controlled by FLL_FRC_NCO_VAL

(Note that this field is required for free-

running FLL modes only)

Table 90 FLL Free-Running Mode

In both cases described above, the FLL must be selected as the CLK_SYS source by setting

SYSCLK_SRC (see Table 80). The free-running FLL modes are not sufficiently accurate for hi-fi ADC

or DAC applications. Note that, in the absence of any reference clock, the FLL output is subject to a

very wide tolerance. See “Electrical Characteristics” for details of the FLL accuracy.

EXAMPLE FLL CALCULATION

To generate 12.288 MHz output (FOUT) from a 12.000 MHz reference clock (FREF):

•

Set FLL_CLK_REF_DIV in order to generate FREF <=13.5MHz:

FLL_CLK_REF_DIV = 00 (divide by 1)

•

Set FLL_OUTDIV for the required output frequency as shown in Table 87:-

FOUT = 12.288 MHz, therefore FLL_OUTDIV = 2h (divide by 8)

•

Set FLL_FRATIO for the given reference frequency as shown in Table 88:

FREF = 12MHz, therefore FLL_FRATIO = 0h (divide by 1)

•

Calculate FVCO as given by FVCO = FOUT x FLL_OUTDIV:-

FVCO = 12.288 x 8 = 98.304MHz

•

Calculate N.K as given by N.K = FVCO / (FLL_FRATIO x FREF):

N.K = 98.304 / (1 x 12) = 8.192

•

Determine FLL_N and FLL_K from the integer and fractional portions of N.K:-

FLL_N is 8. FLL_K is 0.192

•

Confirm that N.K is a fractional quantity and set FLL_FRAC:

N.K is fractional. Set FLL_FRAC = 1.

Note that, if N.K is an integer, then an alternative value of FLL_FRATIO should be

selected in order to produce a fractional value of N.K.

WM8993 Datasheet(PDF) 135 Page - Wolfson Microelectronics plc

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