WM8993 datasheet(134/229 Pages) WOLFSON

134 / 229 page

WM8993

Production Data

PD, November 2010, Rev 4.0

134

FREE-RUNNING FLL CLOCK

The FLL can generate a clock signal even when no external reference is available. However, it

should be noted that the accuracy of this clock is reduced, and a reference source should always be

used where possible. Note that, in free-running modes, the FLL is not sufficiently accurate for hi-fi

ADC or DAC applications. However, the free-running modes are suitable for clocking most other

functions, including the Write Sequencer, Charge Pump, DC Servo and Class D loudspeaker driver.

If an accurate reference clock is initially available, then the FLL should be configured as described

above. The FLL will continue to generate a stable output clock after the reference input is stopped or

disconnected.

If no reference clock is available at the time of starting up the FLL, then an internal clock frequency

of approximately 12MHz can be generated by enabling the FLL Analogue Oscillator using the

FLL_OSC_ENA register bit, and setting FOUT clock divider to divide by 8 (FLL_OUTDIV = 010b), as

defined in Table 89. Under recommended operating conditions, the FLL output may be forced to

approximately 12MHz by then enabling the FLL_FRC_NCO bit and setting FLL_FRC_NCO_VAL to

19h (see Table 90). The resultant CLK_SYS, together with the default settings of DCLK_DIV,

CLK_DCS_DIV and CLK_256K_DIV, delivers the required clock frequencies for the Class D output

driver, DC Servo, Charge Pump and other functions. Note that the value of FLL_FRC_NCO_VAL

may be adjusted to control FOUT, but care should be taken to maintain the correct relationship

between CLK_SYS and the aforementioned functional blocks.

WM8993 Datasheet(PDF) 134 Page - Wolfson Microelectronics plc