WM8993 datasheet(130/229 Pages) WOLFSON

130 / 229 page

WM8993

Production Data

PD, November 2010, Rev 4.0

130

TOCLK_RATE

TOCLK_RATE_X4 TOCLK_RATE_DIV16

TOCLK

FREQ (HZ)

PERIOD (MS)

1000

500

250

125

62.5

31.25

15.625

7.8125

128

Table 86 TOCLK Rates

BCLK AND LRCLK CONTROL

In master mode, BCLK is derived from CLK_SYS via a programmable division set by BCLK_DIV.

In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE.

The BCLK input to this divider may be internal or external, allowing mixed master and slave modes.

The direction of these signals and the clock frequencies are controlled as described in the “Digital

Audio Interface Control” section.

FREQUENCY LOCKED LOOP (FLL)

The integrated FLL can be used to generate CLK_SYS from a wide variety of different reference

sources and frequencies. The FLL can use either MCLK, BCLK or LRCLK as its reference, which

may be a high frequency (eg. 12.288MHz) or low frequency (eg. 32,768kHz) reference. The FLL is

tolerant of jitter and may be used to generate a stable CLK_SYS from a less stable input signal. The

FLL characteristics are summarised in “Electrical Characteristics”.

Note that the FLL can be used to generate a free-running clock in the absence of an external

reference source. This is described in the “Free-Running FLL Clock” section below.

The FLL control registers are illustrated in Figure 60.

Figure 60 FLL Configuration

The FLL is enabled using the FLL_ENA register bit. Note that, when changing FLL settings, it is

recommended that the digital circuit be disabled via FLL_ENA and then re-enabled after the other

recommended that the FLL be reset by setting FLL_ENA to 0.

Note that, for normal operation of the FLLs, the reference voltage VMID and the bias current must

also be enabled. See “Reference Voltages and Master Bias” for details of the associated controls

VMID_SEL and BIAS_ENA.

The field FLL_CLK_REF_DIV provides the option to divide the input reference (MCLK, BCLK or

LRCLK) by 1, 2, 4 or 8. This field should be set to bring the reference down to 13.5MHz or below. For

best performance, it is recommended that the highest possible frequency - within the 13.5MHz limit -

should be selected.

The FLL output frequency is directly determined from FLL_FRATIO, FLL_OUTDIV and the real

number represented by N.K. The integer value N is held in the FLL_N register field (LSB = 1), and is

WM8993 Datasheet(PDF) 130 Page - Wolfson Microelectronics plc

WM8993 Datasheet(HTML) 130 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL