WM8993 datasheet(128/229 Pages) WOLFSON

128 / 229 page

WM8993

Production Data

PD, November 2010, Rev 4.0

128

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clocking 1

8:6

DCLK_DIV

[2:0]

111

Class D Clock Divider

000 = CLK_SYS

001 = CLK_SYS / 2

010 = CLK_SYS / 3

011 = CLK_SYS / 4

100 = CLK_SYS / 6

101 = CLK_SYS / 8

110 = CLK_SYS / 12

111 = CLK_SYS / 16

Note - this field is ignored and invalid in

Automatic Clocking Configuration mode.

R65 (41h)

Clocking 3

13:10

CLK_DCS_DIV

[3:0]

1000

DC Servo Clock Divider

0000 = CLK_SYS

0001 = CLK_SYS / 1.5

0010 = CLK_SYS / 2

0011 = CLK_SYS / 2.5

0100 = CLK_SYS / 3

0101 = CLK_SYS / 4

0110 = CLK_SYS / 5.5

0111 = CLK_SYS / 6

1000 = CLK_SYS / 8

Note - this field is ignored and invalid in

Automatic Clocking Configuration mode.

R66 (42h)

Clocking 4

6:1

CLK_256K_DIV

[5:0]

2Fh

256kHz Clock Divider

0d = CLK_SYS

1d = CLK_SYS / 2

2d = CLK_SYS / 3

….

63d = CLK_SYS / 64

Note - this field is ignored and invalid in

Automatic Clocking Configuration mode.

Table 83 256k, DC Servo, Class D Clock Control

WM8993 Datasheet(PDF) 128 Page - Wolfson Microelectronics plc

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