WM8993 datasheet(129/229 Pages) WOLFSON

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Production Data

WM8993

PD, November 2010, Rev 4.0

129

OPCLK CONTROL

A clock output (OPCLK) derived from CLK_SYS may be output on the GPIO1 pin. This clock is

enabled by register bit OPCLK_ENA, and its frequency is controlled by OPCLK_DIV.

This output of this clock is also dependent upon the GPIO register settings described under “General

Purpose Input/Output”.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

Manageme

nt (2)

OPCLK_ENA

GPIO Clock Output Enable

0 = disabled

1 = enabled

R6 (06h)

Clocking 1

12:9

OPCLK_DIV

[3:0]

0000b

GPIO Output Clock Divider

0000 = CLK_SYS

0001 = CLK_SYS / 2

0010 = CLK_SYS / 3

0011 = CLK_SYS / 4

0100 = CLK_SYS / 5.5

0101 = CLK_SYS / 6

0110 = CLK_SYS / 8

0111 = CLK_SYS / 12

1000 = CLK_SYS / 16

1001 to 1111 = Reserved

Table 84 OPCLK Control

TOCLK CONTROL

A slow clock (TOCLK) is derived from the internally generated 256kHz clock to enable input de-

bouncing and volume update timeout functions. This clock is enabled by register bit TOCLK_ENA,

and its frequency is controlled by TOCLK_RATE, TOCLK_RATE_X4, and TOCLK_RATE_DIV16, as

described in Table 85.

A fixed division of 256kHz / 1024 is applied to generate TOCLK. The final TOCLK frequency may be

a multiple or fraction of this frequency, according to the TOCLK_RATE, TOCLK_RATE_X4, and

TOCLK_RATE_DIV16 register bits.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clocking 1

TOCLK_RATE

TOCLK Rate Divider (/2)

0 = f / 2

1 = f / 1

TOCLK_ENA

TOCLK Enable

0 = disabled

1 = enabled

R66 (42h)

Clocking 4

TOCLK_RATE_

DIV16

TOCLK Rate Divider (/16)

0 = f / 1

1 = f / 16

TOCLK_RATE_

TOCLK Rate Multiplier

0 = f x 1

1 = f x 4

Table 85 TOCLK Control

A list of possible TOCLK rates is provided in Table 86.

WM8993 Datasheet(PDF) 129 Page - Wolfson Microelectronics plc

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