WM8993 datasheet(127/229 Pages) WOLFSON

127 / 229 page

Production Data

WM8993

PD, November 2010, Rev 4.0

127

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14 (0Eh)

ADC CTRL

ADC_OSR128

ADC Oversample Rate Select

0 = disabled

1 = enabled

For 48kHz sample rate, the ADC

oversample rate is 128fs when

ADC_OSR128 is selected. Setting this

bit to 0 selects 64fs mode.

Default is 128fs.

R65 (41h)

Clocking 3

CLK_DSP_ENA

CLK_DSP enable

0 = disabled

1 = enabled

R66 (42h)

Clocking 4

DAC_DIV4

DAC Divide-by-4 select

0 = DAC_DIV

1 = DAC_DIV / 4

Note - this field is ignored and invalid in

Automatic Clocking Configuration mode.

Table 82 ADC / DAC Clock Control

256K, DC SERVO, CLASS D CLOCK CONTROL

Clocking is required to support a variety of other functions on the WM8993, including the DC Servo

and the Class D amplifier. In Manual Clocking Configuration mode, these are controlled using the

automatically by the WM8993.

The DCLK_DIV register controls the Class D amplifier switching frequency. The DCLK_DIV register

should be set to derive a clock frequency of around 768kHz. Note that there is an additional divide by

two in the output stage producing a 384kHz switching frequency. The class D switching clock

frequency should not be altered while the speaker output is active as this may generate an audible

click.

The CLK_DCS_DIV register controls the DC Servo clocking frequency. The CLK_DCS_DIV register

should be set to derive a clock frequency of around 1.5MHz.

The CLK_256K_DIV register controls the 256kHz clocking for other circuits, including the Control

Write Sequencer. The CLK_256K_DIV register should be set to derive a clock frequency of around

256kHz.

WM8993 Datasheet(PDF) 127 Page - Wolfson Microelectronics plc

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