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WM8993 Datasheet(PDF) 123 Page - Wolfson Microelectronics plc |
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WM8993 Datasheet(HTML) 123 Page - Wolfson Microelectronics plc |
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123 / 229 page  Production Data WM8993 w PD, November 2010, Rev 4.0 123 MCLK FLL f/N MCLK_SRC selects master clock source (MCLK pin or GPIO1 pin). FLL_CLK_SRC selects the input reference for FLL oscillator. Internal clocks are derived from CLK_SYS. These are enabled by CLK_SYS_ENA. CLK_SYS can be derived from MCLK or from the FLL output. The CLK_SYS source is selected by SYSCLK_SRC and has a divide by 2 option (MCLKDIV). DSP clocks are derived from CLK_SYS. These are enabled by CLK_DSP_ENA. DAC DSP clock is set by DAC_DIV. This should be set to 256 x Sample Rate in both master or slave modes. Alternate settings are available using DAC_OSR128 in Automatic Clocking Control mode only. ADC DSP clock is set by ADC_DIV. This should be set to 256 x Sample Rate in both master or slave modes. Alternate settings are available using ADC_OSR128. The 256k clock for internal functions is set by CLK_256K_DIV. DC Servo clock is set by CLK_DCS_DIV. This should be set to around 1.5MHz. Class D switching rate is set by DCLK_DIV. This should be set to around 768kHz. Note that there is an additional divide by two in the output stage producing a 384kHz switching frequency. GPIO output clock frequency is set by OPCLK_DIV. The slow clock for volume update timeout and GPIO / accessory detect de-bounce is enabled by TOCLK_ENA. The frequency is set by TOCLK_RATE. BCLK rate is set by BCLK_DIV in master mode. BCLK rate must be high enough to support the higher of the ADC and DAC sample rates. LRCLK rate is set by LRCLK_DIV in master mode. The BCLK input to this divider may be internal or external. In automatic mode (SR_MODE), most of the clock dividers are configured automatically by setting the SAMPLE_RATE and CLK_SYS_RATE. SYSCLK_SRC CLK_SYS_ENA BCLK LRCLK FLL_CLK_SRC R07h[12] MCLK_DIV 0 = MCLK 1 = MCLK / 2 CLK_DSP_ENA ADC_DIV [2:0] ADC DSP f/N ADC R07h[7:5] ADC_DIV[2:0] 000 = CLK_DSP 001 = CLK_DSP / 1.5 010 = CLK_DSP / 2 011 = CLK_DSP / 3 100 = CLK_DSP / 4 101 = CLK_DSP / 5.5 110 = CLK_DSP / 6 111 = Reserved f/N R0Eh[9] ADC_OSR128 0 = f / 4 (64fs) 1 = f / 2 (128fs) DAC DAC_DIV [2:0] DAC DSP R07h[4:2] DAC_DIV2:0] 000 = CLK_DSP 001 = CLK_DSP / 1.5 010 = CLK_DSP / 2 011 = CLK_DSP / 3 100 = CLK_DSP / 4 101 = CLK_DSP / 5.5 110 = CLK_DSP / 6 111 = Reserved f/N Automatic DSP Clocking Control SR_MODE SAMPLE_RATE [2:0] CLK_SYS_RATE [3:0] In Automatic DSP Clocking Mode, the DAC, ADC, 256kHz, DC Servo and Class D clocks are configured automatically according to SAMPLE_RATE and CLK_SYS_RATE. · For digital functionality, CLK_SYS minimum is 64fs (DAC mono), 128fs (DAC stereo) or 256fs (ADC). · For specified noise performance, CLK_SYS minimum is 3MHz (normal mode) or 6MHz (DAC_OSR128 mode). · DAC_OSR128 mode can be selected in Auto mode, by setting DAC_OSR128. · The clock divider control fields are ignored and invalid in Auto Mode. DAC_OSR128 R41h[13:10] CLK_DCS_DIV[3:0] 0000 = CLK_SYS 0001 = CLK_SYS / 1.5 0010 = CLK_SYS / 2 0011 = CLK_SYS / 2.5 0100 = CLK_SYS / 3 0101 = CLK_SYS / 4 0110 = CLK_SYS / 5.5 0111 = CLK_SYS / 6 1000 = CLK_SYS / 8 f/N CLK_DCS_DIV DC Servo clock R06h[8:6] DCLKDIV[2:0] 000 = CLK_SYS 001 = CLK_SYS / 2 010 = CLK_SYS / 3 011 = CLK_SYS / 4 100 = CLK_SYS / 6 101 = CLK_SYS / 8 110 = CLK_SYS / 12 111 = CLK_SYS / 16 f/N DCLKDIV Class D switching clock GPIO Clock Output f/N OPCLK_DIV R06h[12:9] OPCLK_DIV[3:0] 0000 = CLK_SYS 0001 = CLK_SYS / 2 0010 = CLK_SYS / 3 0011 = CLK_SYS / 4 0100 = CLK_SYS / 5.5 0101 = CLK_SYS / 6 0110 = CLK_SYS / 8 0111 = CLK_SYS / 12 1000 = CLK_SYS /16 1001 – 1111 = Reserved OPCLK_ENA R42h[6:1] CLK_256K_DIV[5:0] 000000 = CLK_SYS 000001 = CLK_SYS / 2 000010 = CLK_SYS / 3 …. 111111 = CLK_SYS / 64 f/N CLK_256K_DIV 256kHz clock to Charge Pump and other circuits f.N TOCLK_ENA Button/accessory detect de-bounce, Volume update timeout f/N f/1024 R41h[7] TOCLK_RATE_X4 0 = f x 1 1 = f x 4 R06h[15] TOCLK_RATE 0 = f / 2 1 = f / 1 f/N R42h[9] DAC_DIV4 0 = f / 1 1 = f / 4 N = 1 in Manual mode N >= 1 in DAC_OSR128 (Auto) mode R06h[4:1] BCLK_DIV[3:0] 0000 = CLK_SYS 0001 = CLK_SYS / 1.5 0010 = CLK_SYS / 2 0011 = CLK_SYS / 3 0100 = CLK_SYS / 4 0101 = CLK_SYS / 5.5 0110 = CLK_SYS / 6 0111 = CLK_SYS / 8 1000 = CLK_SYS / 11 1001 = CLK_SYS / 12 1010 = CLK_SYS / 16 1011 = CLK_SYS / 22 1100 = CLK_SYS / 24 1101 = CLK_SYS / 32 1110 = CLK_SYS / 44 1111 = CLK_SYS / 48 BCLK_DIV [3:0] f/N LRCLK_RATE [10:0] LRCLK BCLK MASTER MODE CLOCK OUTPUTS f/N GPIO1 MCLK_SRC MCLK_INV f/N R41h[8] TOCLK_RATE_DIV16 0 = f / 1 1 = f / 16 Figure 59 Clocking Scheme |
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