WM8993 datasheet(122/229 Pages) WOLFSON

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WM8993

Production Data

PD, November 2010, Rev 4.0

122

CLOCKING AND SAMPLE RATES

The internal clocks for the WM8993 are all derived from a common internal clock source, CLK_SYS.

This clock is the reference for the ADCs, DACs, DSP core functions, digital audio interface, Class D

switching amplifier, DC servo control and other internal functions.

CLK_SYS can either be derived directly from MCLK, or may be generated from a Frequency Locked

Loop (FLL) using MCLK, BCLK or LRCLK as a reference. Many commonly-used audio sample rates

can be derived directly from typical MCLK frequencies; the FLL provides additional flexibility for a

wide range of MCLK frequencies. To avoid audible glitches, all clock configurations must be set up

before enabling playback. The FLL can be used to generate a free-running clock in the absence of an

external reference source; see “Frequency Locked Loop (FLL)” for further details.

The WM8993 supports Manual or Automatic clocking configuration modes. In Automatic mode, the

programmable dividers associated with the ADCs, DACs, DSP core functions, Class D switching and

DC servo are configured automatically, with values determined from the CLK_SYS_RATE and

SAMPLE_RATE fields. In Automatic mode, the user must also configure the OPCLK (if required), the

TOCLK (if required) and the digital audio interface. In Manual mode, the entire clocking configuration

can be programmed according to the application requirements.

The ADC and DAC sample rates are independently selectable, relative to CLK_SYS, using ADC_DIV

and DAC_DIV. These fields must be set according to the required sampling frequency. Oversample

rates of 64fs or 128fs are supported (based on a 48kHz sample rate).

A 256kHz clock, supporting a number of internal functions, is derived from CLK_SYS, via a

programmable divider CLK_256K_DIV.

The DC servo control is clocked from CLK_SYS, via a programmable divider CLK_DCS_DIV.

The Class D switching amplifier is clocked from CLK_SYS, via a programmable divider DCLK_DIV.

A GPIO Clock, OPCLK, can be derived from CLK_SYS and output on the GPIO1 pin to provide

clocking to other devices. This clock is enabled by OPCLK_ENA and controlled by OPCLK_DIV.

A slow clock, TOCLK, is used to de-bounce the button/accessory detect inputs, and to set the

timeout period for volume updates when zero-cross detect is used. This clock is enabled by

TOCLK_ENA and controlled by TOCLK_RATE, TOCLK_RATE_X4 and TOCLK_RATE_DIV16.

In master mode, BCLK is derived from CLK_SYS via a programmable divider set by BCLK_DIV. In

master mode, the LRCLK is derived from BCLK via a programmable divider LRCLK_RATE. The

LRCLK can be derived from an internal or external BCLK source, allowing mixed master/slave

operation.

The control registers associated with Clocking and Sample Rates are shown in Table 80 to Table 85.

The overall clocking scheme for the WM8993 is illustrated in Figure 59.

WM8993 Datasheet(PDF) 122 Page - Wolfson Microelectronics plc