WM8993 datasheet(118/229 Pages) WOLFSON

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WM8993

Production Data

PD, November 2010, Rev 4.0

118

Figure 56 Digital Audio Interface Clock Control

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Audio

Interface (1)

BCLK_DIR

BCLK Direction

(Forces BCLK clock to be output in

slave mode)

0 = BCLK normal operation

1 = BCLK clock output enabled

R6 (06h)

Clocking (1)

4:1

BCLK_DIV

0100

BCLK Rate

0000 = CLK_SYS

0001 = CLK_SYS / 1.5

0010 = CLK_SYS / 2

0011 = CLK_SYS / 3

0100 = CLK_SYS / 4

0101 = CLK_SYS / 5.5

0110 = CLK_SYS / 6

0111 = CLK_SYS / 8

1000 = CLK_SYS / 11

1001 = CLK_SYS / 12

1010 = CLK_SYS / 16

1011 = CLK_SYS / 22

1100 = CLK_SYS / 24

1101 = CLK_SYS / 32

1110 = CLK_SYS / 44

1111 = CLK_SYS / 48

R8 (08h)

Audio

Interface (3)

AIF_MSTR1

Audio Interface 1 Master Mode Select

0 = Slave mode

1 = Master mode

R9 (09h)

Audio

Interface (4)

LRCLK_DIR

LRCLK Direction

(Forces LRCLK clock to be output in

slave mode)

0 = LRCLK normal operation

1 = LRCLK clock output enabled

10:0

LRCLK_RATE

[10:0]

040h

LRCLK Rate

LRCLK clock output =

BCLK / LRCLK_RATE

Integer (LSB = 1)

Valid from 8..2047

Table 75 Digital Audio Interface Clock Control

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