WM8993 datasheet(116/229 Pages) WOLFSON

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WM8993

Production Data

PD, November 2010, Rev 4.0

116

Figure 55 TDM in DSP Mode B

DIGITAL AUDIO INTERFACE CONTROL

The register bits controlling audio data format, word length, left/right channel data source and TDM

are summarised in Table 73.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R4 (04h)

Audio

Interface

(1)

AIFADCL_SRC

Left Digital Audio interface source

0 = Left ADC data is output on left channel

1 = Right ADC data is output on left channel

AIFADCR_SRC

Right Digital Audio interface source

0 = Left ADC data is output on right channel

1 = Right ADC data is output on right

channel

AIFADC_TDM

ADC TDM Enable

0 = Normal ADCDAT operation

1 = TDM enabled on ADCDAT

AIFADC_TDM_

CHAN

ADCDAT TDM Channel Select

0 = ADCDAT outputs data on slot 0

1 = ADCDAT output data on slot 1

AIF_BCLK_INV

BCLK Invert

0 = BCLK not inverted

1 = BCLK inverted

Note that AIF_BCLK_INV selects the BCLK

polarity in Master mode and in Slave mode.

AIF_LRCLK_IN

Right, left and I2S modes – LRCLK polarity

0 = normal LRCLK polarity

1 = invert LRCLK polarity

Note that AIF_LRCLK_INV selects the

LRCLK polarity in Master mode and in Slave

mode.

DSP Mode – mode A/B select

0 = MSB is available on 2nd BCLK rising

edge after LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising

edge after LRC rising edge (mode B)

6:5

AIF_WL [1:0]

Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

Note - see “Companding” for the selection of

8-bit mode.

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