WM8993 datasheet(117/229 Pages) WOLFSON

117 / 229 page

Production Data

WM8993

PD, November 2010, Rev 4.0

117

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

4:3

AIF_FMT [1:0]

Digital Audio Interface Format

00 = Right justified

01 = Left justified

10 = I2S Format

11 = DSP Mode

R5 (05h)

Audio

Interface

(2)

AIFDACL_SRC

Left DAC Data Source Select

0 = Left DAC outputs left interface data

1 = Left DAC outputs right interface data

AIFDACR_SRC

Right DAC Data Source Select

0 = Right DAC outputs left interface data

1 = Right DAC outputs right interface data

AIFDAC_TDM

DAC TDM Enable

0 = Normal DACDAT operation

1 = TDM enabled on DACDAT

AIFDAC_TDM_

CHAN

DACDAT TDM Channel Select

0 = DACDAT data input on slot 0

1 = DACDAT data input on slot 1

Table 73 Digital Audio Interface Data Control

AUDIO INTERFACE OUTPUT TRI-STATE

digital audio interface pins will be tri-stated by this function, regardless of the state of other registers

which control these pin configurations.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R9 (09h)

Audio

Interface (4)

AIF_TRIS

Audio Interface Tristate

0 = Audio interface pins operate normally

1 = Tristate all audio interface pins

Table 74 Digital Audio Interface Tri-State Control

BCLK AND LRCLK CONTROL

The audio interface can be programmed to operate in master mode or slave mode using the

AIF_MSTR1 register bit.

In master mode, the BCLK and LRCLK signals are generated by the WM8993 when any of the ADCs

or DACs is enabled. In slave mode, the BCLK and LRCLK clock outputs are disabled by default to

allow another digital audio interface to drive these pins.

It is also possible to force the BCLK or LRCLK signals to be output using BCLK_DIR and

LRCLK_DIR, allowing mixed master and slave modes.

The clock generators for the audio interface are enabled according to the control signals shown in

Figure 56. The BCLK_DIR and LRCLK_DIR fields are defined in Table 75.

The BCLK output can be inverted using the AIF_BCLK_INV register bit. The LRCLK output can be

inverted using the AIF_LRCLK_INV register control.

Note that in Slave mode, when BCLK is an input, the AIF_BCLK_INV register selects the polarity of

the received BCLK signal. Under default conditions, DACDAT input is captured on the rising edge of

BCLK, as illustrated in Figure 4. When AIF_BCLK_INV = 1, DACDAT input is captured on the falling

edge of BCLK.

WM8993 Datasheet(PDF) 117 Page - Wolfson Microelectronics plc

WM8993 Datasheet(HTML) 117 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL