WM8993 datasheet(124/229 Pages) WOLFSON

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WM8993

Production Data

PD, November 2010, Rev 4.0

124

CLK_SYS CONTROL

The MCLK_SRC bit is used to select the MCLK source. The source may be either MCLK or GPIO1.

The selected source may also be inverted by setting the register bit MCLK_INV. Note that it is not

recommended to change the control bit MCLK_INV while the WM8993 is processing data as this

may lead to clocking glitches and signal pop and clicks.

The SYSCLK_SRC bit is used to select the source for CLK_SYS. The source may be either the

selected MCLK source or the FLL output. The selected source may also be adjusted by the

MCLK_DIV divider to generate CLK_SYS. These register fields are described in Table 80. See

“Frequency Locked Loop (FLL)” for more details of the Frequency Locked Loop clock generator.

Note that, in AIF Slave modes (see “Digital Audio Interface”), it is important to ensure that CLK_SYS

is synchronised with the LRCLK input. This can be achieved by selecting an MCLK input that is

derived from the same reference as the LRCLK, or can be achieved by selecting the external BCLK

or LRCLK signals as a reference input to one of the FLLs, as a source for CLK_SYS.

If CLK_SYS is not synchronised with LRCLK, then clicks arising from dropped or repeated audio

samples will occur, due to the inherent tolerances of multiple, asynchronous, system clocks.

The CLK_SYS signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 0 when

reconfiguring clock sources. It is not recommended to change MCLK_SRC or SYSCLK_SRC while

the CLK_SYS_ENA bit is set.

The following operating frequency limits must be observed when configuring CLK_SYS. Failure to

observe these limits will result in degraded noise performance and/or incorrect ADC/DAC

functionality.



CLK_SYS ≤ 12.288MHz



CLK_SYS

≥ 3MHz



If DAC_OSR128 = 1 (Automatic Mode only), then CLK_SYS

≥ 6MHz



If DAC_MONO = 1, then CLK_SYS

≥ 64 x fs



If DAC_MONO = 0, then CLK_SYS

≥ 128 x fs



If ADCL_ENA = 1 or ADCR_ENA = 1 then CLK_SYS

≥ 256 x fs

Note that DAC Mono mode (DAC_MONO = 1) is only valid when one or other DAC is disabled. If

both DACs are enabled, then the minimum CLK_SYS for clocking the DACs is 128 x fs.

The CLK_SYS control register fields are defined in Table 80.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Clocking 2

MCLK_SRC

MCLK Source Select

0 = MCLK pin

1 = GPIO1 pin

SYSCLK_SRC

CLK_SYS Source Select

0 = MCLK

1 = FLL output

MCLK_DIV

MCLK Divider

0 = MCLK

1 = MCLK / 2

MCLK_INV

MCLK Invert

0 = MCLK not inverted

1 = MCLK inverted

R69 (45h)

Bus Control

CLK_SYS_ENA

CLK_SYS enable

0 = disabled

1 = enabled

Table 80 MCLK and CLK_SYS Control

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