WM8993 datasheet(133/229 Pages) WOLFSON

133 / 229 page

Production Data

WM8993

PD, November 2010, Rev 4.0

133

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R60 (3Ch)

FLL Control 1

FLL_FRAC

Fractional enable

0 = Integer Mode

1 = Fractional Mode

1 recommended in all cases

FLL_OSC_ENA

FLL Oscillator Enable

0 = FLL disabled

1 = FLL enabled

(Note that this field is required for free-

running FLL modes only)

FLL_ENA

FLL Enable

0 = FLL disabled

1 = FLL enabled

R61 (3Dh)

FLL Control 2

10:8

FLL_OUTDIV

[2:0]

000

FOUT clock divider

000 = 2

001 = 4

010 = 8

011 = 16

100 = 32

101 = 64

110 = 128

111 = 256

(FOUT = FVCO / FLL_OUTDIV)

2:0

FLL_FRATIO

[2:0]

000

FVCO clock divider

000 = 1

001 = 2

010 = 4

011 = 8

1XX = 16

R62 (3Eh)

FLL Control 3

15:0

FLL_K[15:0]

0000h

Fractional multiply for FREF

(MSB = 0.5)

R63 (3Fh)

FLL Control 4

14:5

FLL_N[9:0]

177h

Integer multiply for FREF

(LSB = 1)

R64 (40h)

FLL Control 5

4:3

FLL_CLK_REF_

DIV [1:0]

00b

FLL Clock Reference Divider

00 = MCLK / 1

01 = MCLK / 2

10 = MCLK / 4

11 = MCLK / 8

MCLK (or other input reference) must

be divided down to <=13.5MHz.

For lower power operation, the

reference clock can be divided down

further if desired.

1:0

FLL_CLK_SRC

[1:0]

10b

FLL Clock source

00 = MCLK

01 = LRCLK

10 = BCLK

11 = Reserved

Table 89 FLL Register Map

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