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WM8993 Datasheet(PDF) 170 Page - Wolfson Microelectronics plc |
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WM8993 Datasheet(HTML) 170 Page - Wolfson Microelectronics plc |
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170 / 229 page ![]() WM8993 Production Data w PD, November 2010, Rev 4.0 170 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 10 LINEOUT2P_E NA 0 LINEOUT2P Line Out and LINEOUT2PMIX Enable 0 = Disabled 1 = Enabled 9 SPKRVOL_EN A 0 SPKMIXR Mixer and SPKRVOL PGA Enable 0 = Disabled 1 = Enabled Note that SPKMIXR and SPKRVOL are also enabled when SPKOUTR_ENA is set. 8 SPKLVOL_EN A 0 SPKMIXL Mixer and SPKLVOL PGA Enable 0 = Disabled 1 = Enabled Note that SPKMIXL and SPKLVOL are also enabled when SPKOUTL_ENA is set. 7 MIXOUTLVOL_ ENA 0 MIXOUTL Left Volume Control Enable 0 = Disabled 1 = Enabled 6 MIXOUTRVOL _ENA 0 MIXOUTR Right Volume Control Enable 0 = Disabled 1 = Enabled 5 MIXOUTL_EN A 0 MIXOUTL Left Output Mixer Enable 0 = Disabled 1 = Enabled 4 MIXOUTR_EN A 0 MIXOUTR Right Output Mixer Enable 0 = Disabled 1 = Enabled 1 DACL_ENA 0 Left DAC Enable 0 = DAC disabled 1 = DAC enabled 0 DACR_ENA 0 Right DAC Enable 0 = DAC disabled 1 = DAC enabled Register 03h Power Management (3) REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R4 (04h) Audio Interface (1) 15 AIFADCL_SRC 0 Left Digital Audio interface source 0 = Left ADC data is output on left channel 1 = Right ADC data is output on left channel 14 AIFADCR_SR C 1 Right Digital Audio interface source 0 = Left ADC data is output on right channel 1 = Right ADC data is output on right channel 13 AIFADC_TDM 0 ADC TDM Enable 0 = Normal ADCDAT operation 1 = TDM enabled on ADCDAT 12 AIFADC_TDM_ CHAN 0 ADCDAT TDM Channel Select 0 = ADCDAT outputs data on slot 0 1 = ADCDAT output data on slot 1 9 BCLK_DIR 0 BCLK Direction (Forces BCLK clock to be output in slave mode) 0 = BCLK normal operation 1 = BCLK clock output enabled 8 AIF_BCLK_INV 0 BCLK Invert |
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