WM8993 datasheet(172/229 Pages) WOLFSON

172 / 229 page

WM8993

Production Data

PD, November 2010, Rev 4.0

172

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0 = disabled

1 = enabled

ADC_COMPM

ODE

ADC Companding Type

0 = μ-law

1 = A-law

LOOPBACK

Digital Loopback Function

0 = No loopback

1 = Loopback enabled (ADC data output is directly

input to DAC data input).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6 (06h)

Clocking 1

TOCLK_RATE

TOCLK Rate Divider (/2)

0 = f / 2

1 = f / 1

TOCLK_ENA

TOCLK Enable

0 = disabled

1 = enabled

12:9

OPCLK_DIV

[3:0]

0000

GPIO Output Clock Divider

0000 = CLK_SYS

0001 = CLK_SYS / 2

0010 = CLK_SYS / 3

0011 = CLK_SYS / 4

0100 = CLK_SYS / 5.5

0101 = CLK_SYS / 6

0110 = CLK_SYS / 8

0111 = CLK_SYS / 12

1000 = CLK_SYS / 16

1001 to 1111 = Reserved

8:6

DCLK_DIV

[2:0]

111

Class D Clock Divider

000 = CLK_SYS

001 = CLK_SYS / 2

010 = CLK_SYS / 3

011 = CLK_SYS / 4

100 = CLK_SYS / 6

101 = CLK_SYS / 8

110 = CLK_SYS / 12

111 = CLK_SYS / 16

Note - this field is ignored and invalid in Automatic

Clocking Configuration mode.

4:1

BCLK_DIV

[3:0]

0100

BCLK Rate

0000 = CLK_SYS

0001 = CLK_SYS / 1.5

0010 = CLK_SYS / 2

0011 = CLK_SYS / 3

0100 = CLK_SYS / 4

0101 = CLK_SYS / 5.5

0110 = CLK_SYS / 6

0111 = CLK_SYS / 8

1000 = CLK_SYS / 11

1001 = CLK_SYS / 12

1010 = CLK_SYS / 16

WM8993 Datasheet(PDF) 172 Page - Wolfson Microelectronics plc

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