DP84910 datasheet(24/32 Pages) NSC

24 / 32 page

Pulse Detector Description (Continued)

The differentiator extracts the timing information from the

peaks of the disk signal The timing of the peaks is pre-

served in the zero-crossing of the signal at the differentiator

output A zero-cross detector is used in conjunction with the

qualification channel to provide noise free encoded data

pulses to the data synchronizer Fully differential circuits are

used throughout the pulse detector to minimize pulse pair-

ing

In order to not interpret noise on the baseline as input data

a hysteresis comparator is used for qualifying the channel

input signal Two pins set the hysteresis level by the appli-

cation of an external voltage One pin sets the hysteresis

level in a data field (SETHYSD) and the other pin sets the

hysteresis level in a servo field (SETHYSS) The SFIELD pin

controls the selection between these pins A resistive divid-

er between supply and ground is typically used to provide

these voltages A switched supply output pin (SVCC) is

available to be used as the supply reference for these divid-

ers The SETHYSD voltage is adjustable in eight steps via

bits in the control register (HYS

VTH0

HYS

VTH1

HYS

VTH2 Bank (11) bits 7 8 9) (see Table IIb)

TABLE IIb Hysteresis Threshold Control

Ctrl Reg Bits

% Qual

HYS

VTH2

HYS

VTH1

HYS

VTH0

111

335

101

425

011

515

001

605

SETHYSD e 450 mV

Two bits in the control register (ERD0 ERD1 Bank (11)

bits 2 3) direct the output of the pulse detector to either the

input of the data synchronizer section the ERDOUT pin or

both (see Table III) A test mode is entered when both of

these control register bits are at a logical high level In this

mode the GCA is put into a fixed gain mode the VCOs are

stopped the CRD input is redirected to act as a clock

source for the synchronizer and the CRC pin as a clock

source for the synthesizer

TABLE III SYNCHPD IO Pin Control

Ctrl Reg

Pins Enabled

Mode

Test

Bank (11)

ERD1

ERD0

ERDOUT

ERDIN

OFF

YES

OFF

YES

OFF

YES

Internal pulse detector feed through to synchronizer is disabled ERDIN is

input to the synchronizer

The pulse detector output pulse width is internally fixed to

approximately 15 ns independent of data rate

Four gated peak detectors are used to detect quadrature

embedded servo bursts When gated on the peak detector

charges an external capacitor to a DC level proportional to

the amplitude of the servo burst The output voltage range

of these detectors is large enough for 7 bits of resolution

The gating and discharge of the servo capacitors are con-

trolled by five TTL level logic pins (S1 S2 S3 S4 and

HOLD) as described by Table IV The servo channel is de-

signed for very low servo offsets and good gain linearity

Two servo difference amplifiers (DIFFAMP1 DIFFAMP2)

have been added to the DP84910 which were not present in

previous NSC integrated read channel circuits The first dif-

ference amplifier (DIFFAMP1) takes the difference between

servo channel 1 (SCAP1) and channel 2 (SCAP2) The sec-

ond difference amplifier (DIFFAMP2) takes the difference

between servo channel 3 (SCAP3) and channel 4 (SCAP4)

These differences are centered around an externally sup-

plied reference voltage at the VDIFF pin This reference

voltage is typically set at one half the supply voltage

Two modes of servo operation are now available track fol-

low and seek modes The control or selection of these

modes are with the servo switches (S1 through S4) and

HOLD pins (see Table IV) The difference between these

modes is the amount of charging time the servo peak detec-

tor needs to reach its final value with the same input condi-

tions The track follow mode has a slower charge time than

the seek mode With a slower charge time the peak detec-

tors will be less sensitive to noise on the servo signal Previ-

ous NSC integrated read channel devices only provided the

track follow mode

An output internal signals mode can be entered by applying

a logical high level to the S2 pin and a logical low level to

the HOLD pin In this mode certain selected internal signals

of the pulse detector are routed to the four servo output pins

(SCAP1 – SCAP4) as observation points These signals in-

clude the fully differential analog output of the differentiator

(SCAP1 and SCAP2 pins) the output of the zero-cross de-

tector at the differentiator output (SCAP3 pin) and the de-

layed qualification signal (SCAP4 pin) This mode is useful

for the system designer while optimizing the implementation

of the pulse detector This mode would not normally be se-

lected in a production drive as it precludes the operation of

these pins for embedded servo use

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