DP84910 datasheet(16/32 Pages) NSC

16 / 32 page

AC Electrical CharacteristicsPulse Detector guaranteed over operating conditions (see table)

unless otherwise specified Minimum andor maximum limits are guaranteed by outgoing testing unless otherwise specified

(Note 1)

Symbol

From Input To Output

Parameter

Conditions

Min

Typ

Max Units

(Note 2)

(Note 12)

trecov(s)

ERDO

u Recovery Time from Write

Enable ERD for Pulse Detector

Output Via Control Register

Mode with Short Mode

Programmed

trecov(l)

ERDO

u Recovery Time from Write

Enable ERD for Pulse Detector

Output Via Control Register

Mode with Long Mode

Programmed

trecov(sleep) SLEEP

u ERDOu Recovery Time from Sleep

Enable ERD for Pulse Detector

300

Output Via Control Register

Mode of Pulse Detector

(Note 10)

trecov(IDLE)

IDLE

ERDO

u Pulse Detector Recovery Time (Notes 3 and 11)

SERVOv

from the IDLE Mode

tcharge

S1 to S4

SCAP1 – Gated Detector Charge Time

(Note 3)

200

340

430

SCAP4

tdischarge

S1 to S4

SCAP1 – Gated Detector Discharge

(Note 4)

SCAP4

Time

tON

S1 to S4

SCAP1 – Gated Detector Turn On Time

(Note 5)

SCAP4

tOFF

S1 to S4

SCAP1 – Gated Detector Turn Off Time

(Note 6)

SCAP4

tpw

ERD0

v Encoded Read Data Output

Enable ERD0 for Pulse Detector

Output via Control Register

Pulse Width

tGT0

SCAP4

v SCAP3u Gate to Time Channel Delay

V(SETHYS) eb01V (Note 7)

105

f e 5 MHz

Delay Step 0

tpp

ERD0

Pulse Pairing

VAMPIN e 100 mVPP f e 33 MHz b175

025

175

Differential (Note 9)

f e 7 MHz

125

025

125

tDS1

SCAP4

u SCAP3u Programmable Channel Delay (Note 8)

Step Size Delay Step 1

tDS2

SCAP4

u SCAP3u Programmable Channel Delay (Note 8)

Step Size Delay Step 2

tDS3

SCAP4

u SCAP3u Programmable Channel Delay (Note 8)

Step Size Delay Step 3

Note 1

All parameters are specified for the following conditions unless otherwise stated The device uses the components described in the AC test setup diagram

(See

Figure 5b ) VREF e 05V VSETHYS e 045V VRG e 03V and f e 25 MHz The control register is set at the initial power up conditions except all sections are

powered on RDIF e 50X CDIF e 180 pF

VIN e 100 mVPP differential

Note 2

The symbol (

u) indicates the rising edge of the pulse is used as reference The symbol (v) indicates the falling edge of the pulse is used as reference

Note 3

Connect 200 pF capacitors to SCAP pins With all external capacitors to SCAP pins discharged measure the time from servo channel enable pins (S1 S2

S3 S4) to 90% of the rising edge of the selected servo channel output fIN e 5 MHz

Note 4

Connect 200 pF capacitors to SCAP pins With all external capacitors to SCAP pins discharged measure the time from the servo channel enable pins (S1

S2 S3 S4) to 90% of the falling edge of the selected servo channel output fIN e 5 MHz

Note 5

With no capacitors connected to the SCAP pins pull 1 mA from each of the SCAP pins Measure the time from the selection of each servo channel (S1 S2

S3 S4) to the voltage on the selected servo output when it increases by 01V

Note 6

With no capacitors connected to the SCAP pins pull 1 mA from each of the SCAP pins Measure the time from the selection of each servo channel (S1 S2

S3 S4) to the voltage on the selected servo output when it decreases by 01V

Note 7

Enable internal pulse detector signals and program the gate channel delay step 0 through the control register tGTO includes time contributions from the

test frequency and delay introduced by the external differentiator components The test frequency contribution is the amount of time from the zero crossing at the

base line to the peak (which for a 5 MHz signal is 100 ns) The theoretical delay introduced by the differentiator components RDIF e 50X and CDIF e 180 pF at

this frequency is 13 ns Consequently the raw gate to channel delay can be found by subtracting off these external contributions to the delay

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