Pin

Description

ANALOG SIGNAL PINS

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60

DATA FIELD AUTOMATIC GAIN CONTROL VOLTAGE INPUT (VAGCIND)

When activated by a logical low level on

the SFIELD pin the voltage at this pin controls the gain of the gain controlled amplifier

62 63

AMPLIFIER INPUTS

2

1 (AMPIN2 AMPIN1)

These inputs accept the preamplified analog coded data signal

read from the disk They are to be externally capacitively coupled from the preamplifier They go to a low impedance

state when WRITE GATE is enabled and remain low impedance for either 17 msor3 4 ms (selectable by control

remove DC offsets accumulated across the amplifier input coupling capacitors during the write mode

64

AGC REFERENCE VOLTAGE INPUT (VREF)

This input provides the reference voltage to the AGC circuit for

controlling the peak-to-peak signal swing at the channel input pins The voltage on this pin corresponds directly to the

peak-to-peak channel input signal level A resistor divider between supply and ground can be used to provide this

voltage The SVCC pin is provided to be used as a supply reference

70

SWITCHED SUPPLY VOLTAGE (SVCC)

This emitter-follower output may be used as the supply for the external VREF

resistor voltage divider and for both the external servo and data hysteresis resistor voltage dividers The voltage at this

71

DISCHARGE CAPACITOR (DISCAP)

A capacitor is tied from this pin to ground to establish an RC time constant which

sets the minimum operational frequency and decay characteristics of the AGC The voltage at this pin can also be used

for dynamic hysteresis Note unlike the DP849192 which requires an RC combination tied to this pin the DISCAP pin

has an internal 10 kX resistor connected to ground Thus only an external capacitor is required to set the RC time

constant

73

VOLTAGE CONTROLLED OSCILLATOR INPUT (VCOI)

This pin is the input to the voltage control block for the

synchronizer VCO and is to be connected to the external loop filter output

74

CHARGE PUMP OUTPUT (CPO)

This pin issues the signal from the synchronizer PLL charge pump and is to be

connected to the external loop filter input

76

RNOMINAL (RNOM)

A resistor connected from this pin to ground sets the synchronizer charge pump current

79

TIMING EXTRACTOR FILTER (TEF)

This pin is the filter node for the synthesizer phase locked loop (PLL) An

external resistor and capacitor loop filter is tied in series between this pin and ground

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