DP84910 datasheet(21/32 Pages) NSC

21 / 32 page

Control Register Description

The control register (CR) is comprised of a thirteen bit serial

shift register (eleven data bits and two address bits) four

banks of eleven bit latches and supporting logic The latch-

es are segmented into four subsections (banks) to allow the

user to loadreload subsets of control bits without having to

enter the entire contents of forty-four bits Information is

strobed into the shift register via the CONTROL REGISTER

DATA (CRD) input on the positive edge of CONTROL REG-

ISTER CLOCK (CRC) input with the CONTROL REGISTER

LATCHSHIFT BAR (CRLS) pin at a logical low state The

data from the shift register is parallel transmitted to one of

the four latch banks when CRLS is given a positive tran-

sition To minimize power consumption the CRLS pin

should be kept at a logical high state except when shifting

data into the control register (When this pin is at a logical

high level power to the shift register is interrupted) The

SLEEP and IDLESERVO pins must be disabled (SLEEP e

high and IDLESERVO e low) in order to enter data into

the control register

Bit positions two through twelve contain the control informa-

tion The last two bits entered into the shift register (posi-

tions zero and one) are the two address bits which select

one of the four latch banks into which the data bits are

loaded Table IIa lists the control register bit names and

briefly describes their functions When the device is first

powered on or the sleep mode is exited all the information

bits are forced to Power-On-Reset (POR) states The CON-

TROL REGISTER DATA OUTPUT (CRDO) pin issues data

from the shift register This output is made available so that

it can be connected to the input of another device’s control

minimize the number of data lines from the controller Even

though all control register latches are preset into known

states when the DP84910 is energized (either by applying

VCC or taking SLEEP high) the shift register flip-flops are in

indeterminate states until valid data is shifted fully through

the register Thus the CRDO data is not valid after power

up until all thirteen bits have been shifted in Also note that if

the CRLS input is given a positive transition after power up

occurs but before valid data has been entered into the shift

be randomly loaded into one of the four banks of latches

Valid data must be loaded into the shift register before

CRLS is given a positive transition

TLF11777 – 7

FIGURE 6 Control Register Block Dlagram

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