Power Down Operation

The DP84910 has several methods available to control or

manage device power consumption Three control register

bits and two pins are provided to control the power status of

elements in this device The control register bits control the

power status of the pulse detector (PD

PWR

DN Bank

(10) bit 4) synchronizer (SYNC

PWR

DN Bank (10) bit

2) and synthesizer (STH

PWR

DN Bank (10) bit 3) The

device is configured to initially power up with the synchroniz-

er synthesizer and pulse detector powered down The con-

trol register power is controlled only by the SLEEP pin

The SLEEP pin is one of the two pins available for power

management This pin powers down all circuitry on the chip

including the control register In this mode the maximum

power supply current is 2 mA The control register latches

are preset into specific states when exiting the sleep mode

The shift register flip-flops however are in indeterminate

states until all 13 bits have been shifted in Note that if the

CRLS input is given a positive transition after exiting the

sleep mode but before valid data has been entered into

the shift register the indeterminate contents of the shift reg-

ister will be randomly loaded into one of the four banks of

latches Although the sleep mode can be safely exited with

the CRLS pin either high or low valid data must be loaded

into the shift register before CRLS is given a positive tran-

sition

The IDLESERVO pin is the second of the two pins avail-

able for power management This pin toggles the device

between the idle and servo modes In the idle mode only

the control register and pulse detector biasing circuitry nec-

essary for a quick recovery from the power down mode are

active In the servo mode the pulse detector portions need-

ed for servo detection are active as well as the control regis-

ter Less than 15 ms is required for the pulse detector to

recover from the idle condition The control register data is

not lost when this pin is toggled This pin does not control

the power status of the synchronizer or synthesizer To

achieve maximum power savings during extended servo-

only activity the synchronizer and synthesizer should be

powered down

TABLE I Selective Power Down Truth Table

SLEEP

Pin

SERVO

IDLE

Pin

Ctrl Reg

Power Status by Block

Bank (10)

B4

B3

B2

PD

CR

SYNCH

SYNTH

SERVO

0

X

X

X

X

OFF

OFF

OFF

OFF

1

1

0

0

0

OFF

ON

ON

ON

1

1

0

0

1

OFF

ON

OFF

ON

1

1

0

1

0

OFF

ON

ON

OFF

1

1

0

1

1

OFF

ON

OFF

OFF

10

0

0

0

ON

ON

ON

ON

1

0

0

0

1

ON

ON

OFF

ON

1

0

0

1

0

ON

ON

ON

OFF

1

0

0

1

1

ON

ON

OFF

OFF

1

X

1

0

0

OFF

ON

ON

ON

1

X

1

0

1

OFF

ON

OFF

ON

1

X

1

1

0

OFF

ON

ON

OFF

1

X

1

1

1

OFF

ON

OFF

OFF

Except for pulse detector circuitry biasing necessary for quick recovery from power down mode

Control register buffers powered down Data in register will not be affected but new data cannot

be loaded into register when IDLESERVO is high

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