TABLE IIa Control Register Definitions

(Continued)

Bit

Bit Name

POR

Block

Function

BANK (10)

8

STR

SIGN

0

SYNC

9

STR0

0

SYNC

Strobe Bit0 (LSB)

10

STR1

0

SYNC

Strobe Bit1

11

STR2

0

SYNC

Strobe Bit2 (MSB)

12

CPRATIO

0

SYNC

Synchronizer Charge Pump Gain Control

BANK (11)

0

CR ADDR0

CR

Control Register Bank Address LSB (1)

1

CR ADDR1

CR

Control Register Bank Address MSB (1)

2

ERD0

0

PDSC

ERD Control Bit 0 (Note 1)

3

ERD1

0

PDSC

ERD Control Bit 1 (Note 1)

4

PREAM

2T

0

SYNC

Select 2T Preamble (3T if low)

5

INV

WG

1

PD

6

SLOW

1

PD

7

HYS

VTH0

1

PD

Hysteresis Voltage Control Bit0 (LSB)

8

HYS

VTH1

0

PD

Hysteresis Voltage Control Bit1

9

HYS

VTH2

1

PD

Hysteresis Voltage Control Bit2 (MSB)

10

SERVO

EQ0

1

FILT

Filter BandwidthEqualization Control-Servo Bit0 (LSB)

11

SERVO

EQ1

1

FILT

Filter BandwidthEqualization Control-Servo Bit1

12

SERVO

EQ2

1

FILT

Filter BandwidthEqualization Control-Servo Bit2 (MSB)

Note 1

When ERD0 and ERD1 are both high the GCA is put into a fixed gain mode The synchronizer and synthesizer are put into test modes where their VCO’s

are driven by external signals

Pulse Detector Description

The purpose of the pulse detector is to convert the timing

information contained in the analog peaks of the disk wave-

form into a digital signal whose leading edge accurately rep-

resents the time position of the analog peaks

Raw disk data from the output of an external read preampli-

fier is capacitively coupled to the inputs of the DP84910’s

gain controlled amplifier (AMPIN1 AMPIN2) These inputs

are switched to low impedance when the WRITE GATE in-

put pin is enabled and stays at a low impedance for either

17 msor3 4 ms after WRITE GATE is disabled The amount

of delay is selectable via a bit in the control register (SLOW

Bank (11) bit 6) During this time any DC offsets accumu-

lated across the input coupling capacitors during the write

mode are removed Also during the write mode the AGC

voltage is held fixed and the input signal to the amplifier is

blocked DC offsets at the output of the amplifier are the

same for read or write modes

The gain controlled amplifier (GCA) accepts signals in the

range of 20 mV to 200 mV peak-to-peak differential and

produces a constant 500 mV peak-to-peak differential sig-

nal at the channel inputs (CHAN1 CHAN2) The channel

input signal amplitude is set by a voltage applied to the

VREF pin There is a one-to-one correspondence between

the voltage applied to the VREF pin and the peak-to-peak

differential signal at the GCA outputs The VREF voltage is

typically set by a voltage divider between supply and

ground A switched supply pin (SVCC) can be used to pro-

vide the supply reference for this divider

The gain of the GCA is controlled by a fast equal-attack

equal decay pattern insensitive exponential responding

automatic gain controlled (AGC) amplifier circuit The AGC

allows for fast settling within 3 ms for a 50% change in the

input signal level The exponential response of the AGC al-

lows the settling time to be independent of the input signal

level The response is pattern insensitive because the

charging or discharging of the AGC capacitor is allowed

only in the presence of a signal Thus large shoulder re-

gions will not cause the AGC voltage to droop A high im-

pedance AGC input pin allows for an AGC hold function with

very little leakage of the AGC capacitors’ charge

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