DP84910 datasheet(30/32 Pages) NSC

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Synchronizer Description (Continued)

TABLE IX Window Strobe Control Table

Control Register Bits Bank (11)

STR2 STR1 STR0 STR

SIGN Typical Window Shift

110

(0250)tVCO b 12 ns

101

(0188)tVCO b 12 ns

100

(0125)tVCO b 12 ns

011

(0062)tVCO b 12 ns

010

12 ns

001

06 ns

none

06 ns

12 ns

(0062)tVCO a 12 ns

(0125)tVCO a 12 ns

(0188)tVCO a 12 ns

(0250)tVCO a 12 ns

Note

Strobe selections not shown in above table are invalid and should not

be used If an invalid state is inadvertently entered SDO will become inde-

terminate though PLL lock (phase comparator activity) will not be affected

Synthesizer Description

The synthesizer block is a phase-locked loop with control

feedback path A single external node (Timing Extractor Fil-

ter or TEF) is provided for passive components for the syn-

thesizer PLL filter The resulting synthesized output fSYNTH

is the code rate clock used for encoding and as a reference

signal for the synchronizer during the non-read mode The

frequency of fSYNTH is the reference input frequency multi-

plied by the modulus of the feedback divider and divided by

the modulus of the input divider

fSYNTH e fREF c Nfeedback Ninput

The input divider modulus Ninput is set via control register

Bank (01) bits 8 – 12 (LSB – MSB respectively) and feed-

back modulus Nfeedback is set via control register Bank

(01) bits 2 – 7 (LSB – MSB respectively) The value of each

N modulus is equal to the binary value of its control word

PLUS 2 This gives the input divider a division range of 3 – 33

and the feedback divider a division range of 3 – 65

Ninput e Binary value of CR Bank (01) bits 8–12 a 2

Nfeedback e Binary value CR Bank (01) bits 2–7 a 2

A zero value control word (all bits low) for either divider is

not allowed (divider operation stops) At VCC power-up the

divider control words are both automatically set to binary 1

and thus the ratio

Nfeedback Ninput e (1 a 2)(1 a 2) e (3)(3) or unity

The synthesizer may be selectively powered-down via a sin-

gle bit in the control register (STH

PWR

DN Bank (10)

bit 3) No control register data is lost during selective power-

down When selective power-down occurs an idle-bias cir-

cuit is activated at the TEF pin which keeps the filter voltage

at a typical operating bias of 2 times VBE (approximately

15V) above ground potential in order to minimize lock re-

covery time at reapplication of power

Note

The synchronizer derives key reference signals from the synthesizer

thus the synthesizer must be powered-on for the synchronizer to

operate properly If the synthesizer is powered-down the synchroniz-

er should be as well

In general to minimize digital switching noise it is advised

that the SYNC CLOCK (SCLK) output be used for all read

write clock purposes and the SYNTH output be left dis-

abled For systems which must use a continuous unmulti-

plexed synthesized master clock the SYNTH output is

made available Should the SYNTH output be employed as

a system clock care should be taken as with all switching

outputs on the DP84910 to minimize capactive loading (use

an external bufferdriver for multiple fan-out applications)

The standard

default VCC power-up condition for the

SYNTH output pin is the disabled mode (logic high state)

This output should always be left disabled if not needed

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