Pin

Description

ANALOG SIGNAL PINS

32

VPHASE

An internally generated voltage is present at his pin to control the Q of the integrated filter An external

34

FILTER CHARGE PUMP OUTPUTVCO INPUT NODE (FCPOVCOI)

This is the filter node for the channel filter PLL

An externaI resistor and capacitor loop filter is tied in series between this pin and ground

37

SERVO CAPACITOR

4 (SCAP4)

This pin is the connection point for the peak detector capacitor for the embedded

servo gated detector The DC level on this capacitor represents the amplitude of one of four servo bursts When the

‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical level on the

HOLD pin the signal on this pin becomes the output of the seIectable delay block in the qualification channel (see

Table IV)

38

SERVO CAPACITOR

3 (SCAP3)

This pin is the connection point for the peak detector capacitor for the embedded

servo gated detector The DC level on this capacitor represents the amplitude of one of four servo bursts When the

‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical level on the

HOLD pin the signal on this pin becomes the output of the time channel zero-cross detector (see Table IV)

39

SERVO CAPACITOR

2 (SCAP2)

This pin is the connection point for the peak detector capacitor for the embedded

servo gated detector The DC level on this capacitor represents the amplitude of one of four servo bursts When the

‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical Ievel on the

HOLD pin the signal on this pin becomes one of the differential outputs of the differentiator (see Table IV)

40

SERVO CAPACITOR

1 (SCAP1)

This pin is the connection point for the peak detector capacitor for the embedded

servo gated detector The DC level on this capacitor represents the amplitude of one of four servo bursts When the

‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical level on the

HOLD pin the signal on this pin becomes one of the differential outputs of the differentiator (see Table IV)

41 42

SERVO DIFFERENCE AMPLIFIERS OUTPUTS

1

2 (DIFAMP1 DIFAMP2)

These low impedance pins issue an

output signal which is the difference in voltage between SCAP4 and SCAP3 pins (DIFAMP2) and SCAP2 and SCAP1

pins (DIFAMP1) These differences will be centered about a reference level set by the voltage on the VDlFF pin

43

SERVO DIFFERENCE VOLTAGE REFERENCE INPUT (VDIFF)

A voltage applied to this pin provides a reference for

the zero-level of the signals issued by the difference amplifiers on DIFAMP1 and DIFAMP2 pins

45 46

DIFFERENTIATOR CAPACITOR NODES

1

2 (DIFC1 DIFC2)

These pins are connection points for the

differentiator components (typically a resistor capacitor and inductor)

48 49

GAIN CONTROLLED AMPLIFIER OUTPUTS

1

2 (AMPOUT1 AMPOUT2)

These pins are complimentary emitter

follower outputs from the gain controlled amplifier They are to be externally capacitively coupIed to the channel filter

inputs (FIN1 FIN2)

50 51

FILTER INPUTS

2

1 (FIN2 FIN1)

These channel filter inputs are to be externally capacitively coupled to the gain

controlled amplifier outputs (AMPOUT1 AMPOUT2)

53 54

FILTER OUTPUTS

1

2 (FOUT1 FOUT2)

These pins are complimentary emitter foIIower outputs from the channeI

filter They are to be externally capacitively coupled to the timing-gating channelAGC senseservo channel inputs

(CHAN1 CHAN2)

55 56

TIMING-GATING CHANNELAGC SENSESERVO INPUTS

2

1 (CHAN2 CHAN1)

These input pins are to be

externally capacitively coupled from the channel filter outputs (FOUT1 FOUT2) These pins are the inputs to the

differentiator AGC amplifier servo channel and qualification channel

57

SET HYSTERESIS INPUT-SERVO FIELD (SETHYSS)

When activated by a logical high level on the SFIELD pin the

voltage applied to this pin determines the amount of hysteresis for the pulse detector’s hysteresis comparator This

level should be set high enough to eliminate noise which might occur in the shoulder region between read pulses from

the preamplifier The SVCC pin is provided to be used as a supply reference for a resistive divider to set this level

58

SET HYSTERESIS INPUT-DATA FIELD (SETHYSD)

When activated by a logical low level on the SFlELD pin the

voltage applied to this pin in conjunction with three control register bits (HYS

VTH0 HYS

VTH1 HYS

VTH2

Bank (11) bits 7 8 9) determines the amount of hysteresis for the pulse detector’s hysteresis comparator This level

should be set high enough to eliminate noise which might occur in the shouIder region between read pulses from the

preamplifier The SVCC pin is provided to be used as a supply reference for a resistive divider to set this level

59

SERVO FIELD AUTOMATIC GAIN CONTROL VOLTAGE INPUT (VAGCINS)

When activated by a logical high level

on the SFIELD pin the voltage at this pin controls the gain of the gain controlled amplifier

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