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DP84910 Datasheet(PDF) 22 Page - National Semiconductor (TI) |
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DP84910 Datasheet(HTML) 22 Page - National Semiconductor (TI) |
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22 / 32 page ![]() Control Register Description (Continued) TABLE IIa Control Register Definitions Bit Bit Name POR Block Function BANK (00) 0 CR ADDR0 CR Control Register Bank Address LSB (0) 1 CR ADDR1 CR Control Register Bank Address MSB (0) 2 FILT 3dB 0 1 FILT Channel Filter Cutoff Frequency Selection Bit0 (LSB) 3 FILT 3dB 1 1 FILT Channel Filter Cutoff Frequency Selection Bit1 4 FILT 3dB 2 1 FILT Channel Filter Cutoff Frequency Selection Bit2 5 FILT 3dB 3 1 FILT Channel Filter Cutoff Frequency Selection Bit3 6 FILT 3dB 4 0 FILT Channel Filter Cutoff Frequency Selection Bit4 7 FILT 3dB 5 1 FILT Channel Filter Cutoff Frequency Selection Bit5 8 FILT 3dB 6 1 FILT Channel Filter Cutoff Frequency Selection Bit6 (MSB) 9 EQ0 1 PD Equalization Select Bit0 (LSB) 10 EQ1 0 PD Equalization Select Bit1 11 EQ2 0 PD Equalization Select Bit2 (MSB) 12 SERVO 0 PD Disable BWEQ Control Servo Field (0 e Disable) BANK (01) 0 CR ADDR0 CR Control Register Bank Address LSB (1) 1 CR ADDR1 CR Control Register Bank Address MSB (0) 2 PDATA0 1 SYNTH Feedback Divider Bit0 (LSB) 3 PDATA1 0 SYNTH Feedback Divider Bit1 4 PDATA2 0 SYNTH Feedback Divider Bit2 5 PDATA3 0 SYNTH Feedback Divider Bit3 6 PDATA4 0 SYNTH Feedback Divider Bit4 7 PDATA5 0 SYNTH Feedback Divider Bit5 (MSB) 8 PDATA6 1 SYNTH Input Divider Bit0 (LSB) 9 PDATA7 0 SYNTH Input Divider Bit1 10 PDATA8 0 SYNTH Input Divider Bit2 11 PDATA9 0 SYNTH Input Divider Bit3 12 PDATA10 0 SYNTH Input Divider Bit4 (MSB) BANK (10) 0 CR ADDR0 CR Control Register Bank Address LSB (0) 1 CR ADDR1 CR Control Register Bank Address MSB (1) 2 SYNC PWR DN 1 SYNC Selective Power Down of Synchronizer (Power Down e High) 3 STH PWR DN 1 SYNTH Selective Power Down of Synthesizer (Power Down e High) 4PD PWR DN 1 PD Selective Power Down of Pulse Detector (Power Down e High) 5 ENSTHO 1 SYNTH Enable SYNTH Output (when low) 6 GATE DEL1 0 PD Gating Channel Delay Select Bit 1(LSB) 7 GATE DEL2 1 PD Gating Channel Delay Select Bit 2(MSB) http www nationalcom 22 |
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