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ML7033 Datasheet(PDF) 7 Page - LAPIS Semiconductor Co., Ltd. |
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ML7033 Datasheet(HTML) 7 Page - LAPIS Semiconductor Co., Ltd. |
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7 / 52 page  FEDL7033-04 ML7033 7/52 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power Supply Voltage VDD VDDD, VDDA –0.3 to +7.0 V Analog Input Voltage VAIN — –0.3 to VDD+0.3 V Digital Input Voltage VDIN — –0.3 to VDD+0.3 V Storage Temperature TSTG — –55 to +150 C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Power Supply Voltage VDD Voltage to be fixed; VDDD, VDDA 4.75 5.0 5.25 V Operating Temperature TOP — –40 — +85 C High Level Input Voltage VIH 2.2 — VDD V Low Level Input Voltage VIL All digital input pins 0 — 0.8 V MCK = 2.048 MHz MCKSEL (CR0-B5) bit = “0” –0.01% 2048 +0.01% kHz MCK Frequency FMCK MCK = 4.096 MHz MCKSEL (CR0-B5) bit = “1” –0.01% 4096 +0.01% kHz BCLK Frequency FBCLK BCLK 256 — 4096 kHz Sync Pulse Frequency FSYNC XSYNC, RSYNC –0.01% 8 +0.01% kHz Clock Duty Ratio DCLK MCK,BCLK 40 50 60 % Digital Input Rise Time tIR — — 50 ns Digital Input Fall Time tIF All digital input pins — — 50 ns MCK to BCLK Phase Difference tMB MCK, BCLK — — 50 ns tXS BCLK to XSYNC 50 — — ns Transmit Sync Pulse Setting Time tSX XSYNC to BCLK 50 — — ns tRS BCLK to RSYNC 50 — — ns Receive Sync Pulse Setting Time tSR RSYNC to BCLK 50 — — ns XSYNC, RSYNC SHORT (CR0-B4) bit = “0” 1 BCLK — 125 s –1BCLK s Sync Pulse Width tWS XSYNC, RSYNC SHORT (CR0-B4) bit = “0” 210 — 1BCLK ns PCMOUT Set-up Time tDS PCMOUT 50 — — ns PCMOUT Hold Time tDH PCMOUT 50 — — ns RDL Pull-up Resistor, PCMOUT 0.5 — — k CDL1 PCMOUT — — 50 pF Digital Output Load CDL2 Other output pins — — 50 pF Bypass Capacitor for SGC CSG SGC to AG 0.1 — — F |
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