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ML7033 Datasheet(PDF) 34 Page - LAPIS Semiconductor Co., Ltd. |
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ML7033 Datasheet(HTML) 34 Page - LAPIS Semiconductor Co., Ltd. |
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34 / 52 page ![]() FEDL7033-04 ML7033 34/52 CR7 (CH1 Tone generator 2 control 1) B7 B6 B5 B4 B3 B2 B1 B0 CR7 AOUT1 SEL CH1TG 2 TX CH1TG 2 TOUT1 CH1TG2 LV3 CH1TG2 LV2 CH1TG2 LV1 CH1TG2 LV0 CH1TG2 _8 default 0 0 0 0 0 0 0 0 CR8 (CH1 Tone generator 2 control 2) B7 B6 B5 B4 B3 B2 B1 B0 CR8 CH1TG2 _7 CH1TG2 _6 CH1TG2 _5 CH1TG2 _4 CH1TG2 _3 CH1TG2 _2 CH1TG2 _1 CH1TG2 _0 CR7-B7 … AOUT1P, AOUT1N output select 0 : Single-ended output with the AOUT1P pin with the AOUT1N pin at high impedance 1 : Differential output with the AOUT1P and the AOUT1N pins B6 … CH1 tone generator output select 0 : to Rx side 1 : to Tx side B5 … CH1 tone generator Rx side output pin select 0 : AOUT1 pin 1 : TOUT1 pin B4 to B1 … CH1 Tone Generator 2 (TG2) output level setting This 4-bit field defines the output level for TG2 on CH1 as shown in Table 10. Table 10 TG2 Level Setting B4 (TG2LV3) B3 (TG2LV2) B2 (TG2LV1) B1 (TG2LV0) Level (dBm0) 0 0 0 0 OFF 0 0 0 1 –12.0 0 0 1 0 –11.0 0 0 1 1 –10.0 0 1 0 0 –9.0 0 1 0 1 –8.0 0 1 1 0 –7.0 0 1 1 1 –6.0 1 0 0 0 –5.0 1 0 0 1 –4.0 1 0 1 0 –3.0 1 0 1 1 –2.0 1 1 0 0 –1.0 1 1 0 1 0.0 1 1 1 0 +1.0 1 1 1 1 +2.0 |
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