ML7033 datasheet(30/52 Pages) LAPIS

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FEDL7033-04

ML7033

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CR4 (Debounced timer setting)

CR4

DET2

TIM3

DET2

TIM2

DET2

TIM1

DET2

TIM0

DET1

TIM3

DET1

TIM2

DET1

TIM1

DET1

TIM0

default

B7 to B4

… Debounce timer setting for CH2

B3 to B0

… Debounce timer setting for CH1

To avoid the unintended detection of glitches on the

DETn signal, the ML7033 is equipped with

a debounce timer to hold the

DETn (CR6-B1/CR13-B1) bit and the INT output state for a set

period, even when the state of the

DETn pin changes from logic “1” to logic “0”. Bits B7 to B4

determine the debounce timer setting for CH2. Bits B3 to B0 determine the debounce timer

setting CH1.

The debounce timer is operational only in the power-on state when the

PDN pin = logic “1”,

and remains operational in the power-saving mode with the MODEn (CR0-B1, B0) bits = “0” as

long as the device is in the power-on state.

The debounce timer holding time ranges from 0 ms to 225 ms at 15 ms intervals for each

individual channel. The values written into B7 to B4 (channel 2) or B3 to B0 (channel 1)

determine the holding time for each channel.

The timer value is calculated by the equation of [Decimal(B7,B6,B5,B4) * 15] or

[Decimal(B3,B2,B1,B0) * 15].

Refer to Table 8.

Table 8

Debounce Timer Setting

B7/B3

B6/B2

B5/B1

B4/B0

Timer (ms)

105

120

135

225

ML7033 Datasheet(PDF) 30 Page - LAPIS Semiconductor Co., Ltd.

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