ML7033 datasheet(48/52 Pages) LAPIS

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FEDL7033-04

ML7033

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CR18 (Test control)

CR18

CH2

LOOP1

CH2

LOOP0

CH1

LOOP1

CH1

LOOP0

TEST3

TEST2

TEST1

TEST0

default

B7, B6

… CH2 loop-back test mode select

(B7, B6):

(0, 0) = Loop-back OFF

(0, 1) = Loop-back OFF

(1, 0) = Channel 2 digital loop-back test. PCM data output on the PCMOUT pin during

normal operation is internally looped back through the Receive path via the

PCMIN pin. In digital loop-back test mode, input data on PCMIN pin is ignored,

but PCM data continues to be output on the PCMOUT pin.

(1, 1) = Channel 2 analog loop-back test. Analog signals output on the AOUT2P pin (or the

AOUT2P and AOUT2N pins) are internally looped back to the transmit path

behind a built-in feedback amplifier located after the AIN2P, AIN2N and GSX2

pins. In this mode, the AIN2P and AIN2N input pins are ignored. However, analog

signals continue to be output on the AOUT2P pin (or the AOUT2P and the

AOUT2N pins).

A loop-back test is functional only if XSYNC and RSYNC are from the same clock source.

B5, B4

… CH1 loop-back test mode select

(B5, B4):

(0, 0) = Loop-back OFF

(0, 1) = Loop-back OFF

(1, 0) = Channel 1 digital loop-back test. PCM data is output on the PCMOUT pin in

normal operation is internally looped back through the Receive path via the

PCMIN pin. In loop-back test mode, input data on PCMIN pin is ignored. However,

PCM data can be output on the PCMOUT pin.

(1, 1) = Channel 1 analog loop-back test. Analog signals output on the

AOUT1P pin (or

from the AOUT1P and the AOUT1N pins) are internally looped back to the

transmit path via a built-in feedback amplifier located after the AIN1P, AIN1N and

GSX1 pins. In this mode, the AIN1P and AIN1N input pins are ignored. However,

analog signals can be output from the AOUT1P pin (or from the AOUT1P and the

AOUT1N pins).

A loop-back test is functional if XSYNC and RSYNC are from the same clock source.

B3 to B0

… LSI test registers for an LSI manufacturer

The default alternation is prohibited. When a write action is executed for CR18, set all of

these bits to “0”.

ML7033 Datasheet(PDF) 48 Page - LAPIS Semiconductor Co., Ltd.

ML7033 Datasheet(HTML) 48 Page - LAPIS Semiconductor Co., Ltd.

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