ML7033 datasheet(22/52 Pages) LAPIS

22 / 52 page

FEDL7033-04

ML7033

22/52

Table 6

SLIC Device Operation Mode and Detector Mode

Operating Mode

F2_n

F1_n

F0_n

E0_n = 1

E0_n = 0

Description

Low Power Standby

SHD

GKD

Standby mode

Forward Active

SHD

GKD

Forward battery loop feed

Unbalanced Ringing

RTD

Unbalanced ringing mode

Reverse Active

SHD

GKD

Reverse battery loop feed

Ringing

RTD

Balanced ringing mode

Forward Loop Back

SHD

GKD

Test mode

Tip Open

SHD

GKD

For PBX type application

Power Denial

n/a

Device shutdown

SHD: Switch Hook Detection RTD: Ring Trip Detection GKD:Ground Key Detection

BSEL1, BSEL2

The BSELn pin is the battery mode selection data output. This pin is used when the SLIC connected to the

corresponding channel is an Intersil RSLIC

TM series SLIC device. A logic “0” on this pin selects the low battery

mode, and the logic “1” selects the high battery mode within the SLIC device. The output levels from the BSELn

pins are determined by the BSELn register bits (CR6-B3/CR13-B3).

By connecting these outputs directly to the corresponding SLIC device input pins, battery mode selection of the

SLIC is possible. This pin remains functional even in power-down mode.

SWC1, SWC2

The

SWCn pin is the uncommitted switch control data output. This pin is used when the SLIC connected to the

corresponding channel is an Intersil RSLIC

TM series SLIC device. By connecting this pin directly to the

corresponding input pin of the SLIC device, the uncommitted switch control can be made. The uncommitted

switch is located between the SW+ pin and the SW- pin. A logic “0” on this pin enables the SLIC internal switch

on, and a logic “1” disables the switch.

The output levels from the

SWC1 and SWC2 pins are determined by the SWCn register bits

(CR6-B4/CR13-B4). This pin remains functional even in power-down mode with the

PDN pin is a logic “0”.

DET1, DET2

The

DETn pins are the SLIC’s detection signal (switch hook, ring trip or ground key detection) inputs. These

pins are used when the SLIC connected to the corresponding channel is an Intersil RSLIC

TM series device. A

logic “0” on this pin clears the corresponding

DETn register bit (CR6-B1/CR13-B1). A logic ‘1’ on this pin

input sets the register bit.

The Intersil RSLIC

TM series SLIC device is equipped with a function to switch the output on its

DET pin from a

logic “1” state to a logic “0” state when it detects an assigned event of either off-hook, ring trip or ground key.

Therefore, by connecting these pins to the corresponding pins on the SLIC device and reading the

DETn register

bit (CR6-B1/CR13-B1), the occurrence of an assigned event can be detected.

ML7033 Datasheet(PDF) 22 Page - LAPIS Semiconductor Co., Ltd.

ML7033 Datasheet(HTML) 22 Page - LAPIS Semiconductor Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL