ML7033 datasheet(29/52 Pages) LAPIS

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FEDL7033-04

ML7033

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CR3 (Time slot assignment control)

CR3

TSAE

TSAC

TSA5

TSA4

TSA3

TSA2

TSA1

TSA0

default

* CR3 is a write only register.

… Time slot assignment customization enable

0 : Default time slot assignment

1 : Customized time slot assignment

The default time slot assignment is CH1 for Slot 0 and CH2 for Slot 2.

… Time slot assignment channel select

0 : CH1

1 : CH2

This bit is used to specify the channel for which the accompanied TSAn

(CR3-B5 to B0) bits are going to assign a time slot. Hence, when a customized time slot

assignment is enabled, CR3 should be written twice; once for CH1 and another for CH2.

B5 to B0

… Assigned time slot select

Each time slot consists of 8 BCLK cycles. The number of time slots available for time slot

assignment depends upon the applied BCLK frequency, and can be calculated in the

following equations;

Number of time slots available for time slot assignment

= (BCLK frequency)/(SYNC frequency)/8

= (BCLK frequency)/64k

For instance, when the BCLK frequency is 4096 kHz, time slots that can be assigned are

from 0 (000000) to 63 (111111). The specification of a time slot beyond 63 is prohibited.

Note that in 14-bit linear PCM (2’s complement) mode, specified when the LIN bit

(CR0-B3) is set, only even numbered time slots (0, 2, 4, … 62) can be assigned.

In any mode, the assigned time slot for a channel is common both for transmit and receive,

and different time slots cannot be assigned for transmit and receive. When the TSAE bit

(CR3-B7) is cleared, the time slot assignment specified by these bits is ignored, and the

default time slots are assigned (CH1 for Time Slot 0 and CH2 for Time Slot 2). Figure 12

shows an example of how CH1 is assigned for Time Slot 0 (000000) and CH2 is assigned

for Time Slot 3 (000011) in 8-bit PCM mode.

BCLK

XSYNC

PCMOUT/

PCMIN

PCMOSY

CH1 PCM DATA

CH2 PCM DATA

Slot 0

Slot 1

Slot 2

Slot 3

Figure 12

Example of Time Slot Assignment: CH1 = Slot 0, CH2 = Slot 3

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