PM5347 datasheet(234/302 Pages) PMC

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PM5347 S/UNI-PLUS

DATA SHEET

PMC-941033

ISSUE 6

SATURN USER NETWORK INTERFACE PLUS

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

218

matched load. Normal TTL-type design rules are not recommended and will

reduce the performance of the device.

12.2

Interfacing to ECL or PECL Devices

Although the TXD+/- outputs are TTL compatible, only a few passive components

are required to convert the signals to ECL (or PECL) logic levels. Figure 10

illustrates the recommended configuration. The capacitors AC couple the

outputs so that the ECL inputs are free to swing around the ECL bias voltage

(VBB). The combination of the 237 Ω and 50 Ω resistors divide the voltage down

to a nominally 800mV swing. The 50

Ω resistors also terminate the signals.

Similarly, the RXD+/- inputs to the S/UNI-PLUS are AC coupled as shown in

Figure 10. The S/UNI-PLUS inputs are self-biasing to improve operating speed

and waveform symmetry. For this reason, the DC blocking capacitors are always

required, even when interfacing to PECL drivers. The only exception are the

ALOS+/- inputs which must be DC coupled because of their low frequency

content.

Ceramic coupling capacitors are recommended.

Figure 10

- Interfacing S/UNI-PLUS to ECL or PECL

Zo=50

Ω

S/UNI-PLUS

TXD+

TXD-

10nF

237

Ω

50 Ω

Zo=50

Ω

10nF

237

Ω

50 Ω

ECL

BUFFER

S/UNI-PLUS Driving ECL or PECL

Zo=50

Ω

ECL

BUFFER

RXD+

RXD-

10nF

100 Ω

Zo=50

Ω

10nF

330

Ω

S/UNI-PLUS

330 Ω

ECL or PECL Driving S/UNI-PLUS

12.3

Driving Differential Inputs Single Ended

In some applications it may be more cost effective or technically desirable to

drive the RRCLK+/-, TRCLK+/- or ALOS+/- inputs with a single ended PECL,

TTL or CMOS signal. Figure 11 illustrates the suggested configuration to

achieve this.

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